[Cryptech-Commits] [user/sra/aes_merged] 35/45: Shaved off another cycle for block processing.
git at cryptech.is
git at cryptech.is
Wed Jan 9 16:32:52 UTC 2019
This is an automated email from the git hooks/post-receive script.
sra at hactrn.net pushed a commit to branch master
in repository user/sra/aes_merged.
commit fd40ab87a7f13dd4ce6d636edd7bf7cffc265aa3
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Sat May 26 13:26:20 2018 +0200
Shaved off another cycle for block processing.
---
README.md | 10 +++++-----
src/rtl/aes.v | 15 ++-------------
2 files changed, 7 insertions(+), 18 deletions(-)
diff --git a/README.md b/README.md
index 39f5651..0d552dd 100644
--- a/README.md
+++ b/README.md
@@ -40,17 +40,17 @@ Number of cycles for the old Cryptech AES core:
- AES-256 Decipher one block with key expansion: 77
Number of cycles for the Cryptech AES speed core:
-- AES-128 Encipher one block with key expansion: 17
-- AES-255 Decipher one block with key expansion: 21
+- AES-128 Encipher one block with key expansion: 16
+- AES-255 Decipher one block with key expansion: 20
## Implementation comparison
Implementation results for Xilinx Artix7-t200.
Old Cryptech AES core:
-- 2102 slices
-- 2991 regs
-- 113 MHz (8.79ns)
+- 2094 slices
+- 2854 regs
+- 114 MHz (8.76ns)
Cryptec AES speed core:
diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index 0d719d2..ddee8f0 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -107,10 +107,6 @@ module aes(
reg [31 : 0] key_reg [0 : 7];
reg key_we;
- reg [127 : 0] result_reg;
- reg valid_reg;
- reg ready_reg;
-
//----------------------------------------------------------------
// Wires.
@@ -189,16 +185,9 @@ module aes(
next_reg <= 1'b0;
encdec_reg <= 1'b0;
keylen_reg <= 1'b0;
-
- result_reg <= 128'h0;
- valid_reg <= 1'b0;
- ready_reg <= 1'b0;
end
else
begin
- ready_reg <= core_ready;
- valid_reg <= core_valid;
- result_reg <= core_result;
init_reg <= init_new;
next_reg <= next_new;
@@ -259,7 +248,7 @@ module aes(
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
- ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg};
+ ADDR_STATUS: tmp_read_data = {30'h0, core_valid, core_ready};
default:
begin
@@ -267,7 +256,7 @@ module aes(
endcase // case (address)
if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
- tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
+ tmp_read_data = core_result[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
end
end
end // addr_decoder
More information about the Commits
mailing list