[Cryptech-Commits] [user/sra/aes_merged] 33/45: Updated README with latest implementation results and status for the core.

[git at cryptech.is]

This is an automated email from the git hooks/post-receive script.

sra at hactrn.net pushed a commit to branch master
in repository user/sra/aes_merged.

commit 74e0f67e0a1a694fc93e99b9d1ae71ebfe9bcf55
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Tue May 22 13:15:15 2018 +0200

    Updated README with latest implementation results and status for the core.
---
 README.md | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/README.md b/README.md
index aa2e14e..39f5651 100644
--- a/README.md
+++ b/README.md
@@ -10,16 +10,13 @@ is to allow a drop-in replacement in Cryptech designs.
 
 
 ## Status ##
-First round of optimizations done. Core similates correctly. Has not
-yet been implemented in FPGA.
+Second round of optimizations done. Core similates correctly. Core has
+been implemented in FPGA, but not functionally tested in real HW.
 
 
 ## Introduction ##
 This implementation supports 128 and 256 bit keys. The
-implementation is iterative and process one 128 block at a time. Blocks
-are processed on a word level with 4 S-boxes in the data path. The
-S-boxes for encryption are shared with the key expansion and the core
-can thus not do key update in parallel with block processing.
+implementation is iterative and process one 128 block at a time.
 
 The encipher and decipher block processing datapaths are separated and
 basically self contained given access to a set of round keys and a
@@ -34,7 +31,7 @@ S-boxes for decipher. This allows the core to perform the SubBytes and
 InverseSubBytes operations in the AES round functions in one cycle.
 
 The key expansion does not share S-boxes with the encipher datapath, so
-the total number of S-boxes is 20.
+the total number of S-boxes is 40.
 
 
 ## Performance comparison
@@ -57,6 +54,6 @@ Old Cryptech AES core:
 
 
 Cryptec AES speed core:
-- 2076 slices
+- 2112 slices
 - 2984 regs
-- 117 MHz. (8.54ns)
+- 116 MHz. (8.62ns)