[Cryptech-Commits] [core/hash/sha512] branch master updated: Locked down API write and API digest read access to only be allowed when the core is ready and not busy doing processing.

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joachim at secworks.se pushed a commit to branch master
in repository core/hash/sha512.

The following commit(s) were added to refs/heads/master by this push:
     new d97c71c  Locked down API write and API digest read access to only be allowed when the core is ready and not busy doing processing.
d97c71c is described below

commit d97c71c3ec62a881b7632db29f15550c9ca374e9
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Fri Oct 19 14:08:35 2018 +0200

    Locked down API write and API digest read access to only be allowed when the core is ready and not busy doing processing.
---
 src/rtl/sha512.v | 116 +++++++++++++++++++++++++++----------------------------
 1 file changed, 58 insertions(+), 58 deletions(-)

diff --git a/src/rtl/sha512.v b/src/rtl/sha512.v
index 085783b..6356a8c 100644
--- a/src/rtl/sha512.v
+++ b/src/rtl/sha512.v
@@ -318,84 +318,86 @@ module sha512(
         begin
           if (we)
             begin
-              if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK31))
-                block_we = 1'h1;
+              if (core_ready)
+                begin
+                  if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK31))
+                    block_we = 1'h1;
 
-              case (address)
-                ADDR_CTRL:
-                  begin
-                    init_new        = write_data[CTRL_INIT_BIT];
-                    next_new        = write_data[CTRL_NEXT_BIT];
-                    mode_new        = write_data[CTRL_MODE_HIGH_BIT : CTRL_MODE_LOW_BIT];
-                    mode_we         = 1'h1;
-                    work_factor_new = write_data[CTRL_WORK_FACTOR_BIT];
-                    work_factor_we  = 1'h1;
-                  end
+                  case (address)
+                    ADDR_CTRL:
+                      begin
+                        init_new        = write_data[CTRL_INIT_BIT];
+                        next_new        = write_data[CTRL_NEXT_BIT];
+                        mode_new        = write_data[CTRL_MODE_HIGH_BIT : CTRL_MODE_LOW_BIT];
+                        mode_we         = 1'h1;
+                        work_factor_new = write_data[CTRL_WORK_FACTOR_BIT];
+                        work_factor_we  = 1'h1;
+                      end
 
-                ADDR_WORK_FACTOR_NUM:
-                  begin
-                    work_factor_num_we = 1;
-                  end
+                    ADDR_WORK_FACTOR_NUM:
+                      begin
+                        work_factor_num_we = 1;
+                      end
 
-                ADDR_DIGEST0:
-                  state00_we = 1;
+                    ADDR_DIGEST0:
+                      state00_we = 1;
 
-                ADDR_DIGEST1:
-                  state01_we = 1;
+                    ADDR_DIGEST1:
+                      state01_we = 1;
 
-                ADDR_DIGEST2:
-                  state02_we = 1;
+                    ADDR_DIGEST2:
+                      state02_we = 1;
 
-                ADDR_DIGEST3:
-                  state03_we = 1;
+                    ADDR_DIGEST3:
+                      state03_we = 1;
 
-                ADDR_DIGEST4:
-                  state04_we = 1;
+                    ADDR_DIGEST4:
+                      state04_we = 1;
 
-                ADDR_DIGEST5:
-                  state05_we = 1;
+                    ADDR_DIGEST5:
+                      state05_we = 1;
 
-                ADDR_DIGEST6:
-                  state06_we = 1;
+                    ADDR_DIGEST6:
+                      state06_we = 1;
 
-                ADDR_DIGEST7:
-                  state07_we = 1;
+                    ADDR_DIGEST7:
+                      state07_we = 1;
 
-                ADDR_DIGEST8:
-                  state08_we = 1;
+                    ADDR_DIGEST8:
+                      state08_we = 1;
 
-                ADDR_DIGEST9:
-                  state09_we = 1;
+                    ADDR_DIGEST9:
+                      state09_we = 1;
 
-                ADDR_DIGEST10:
-                  state10_we = 1;
+                    ADDR_DIGEST10:
+                      state10_we = 1;
 
-                ADDR_DIGEST11:
-                  state11_we = 1;
+                    ADDR_DIGEST11:
+                      state11_we = 1;
 
-                ADDR_DIGEST12:
-                  state12_we = 1;
+                    ADDR_DIGEST12:
+                      state12_we = 1;
 
-                ADDR_DIGEST13:
-                  state13_we = 1;
+                    ADDR_DIGEST13:
+                      state13_we = 1;
 
-                ADDR_DIGEST14:
-                  state14_we = 1;
+                    ADDR_DIGEST14:
+                      state14_we = 1;
 
-                ADDR_DIGEST15:
-                  state15_we = 1;
+                    ADDR_DIGEST15:
+                      state15_we = 1;
 
-                default:
-                  begin
-                    tmp_error = 1;
-                  end
-              endcase // case (address)
+                    default:
+                      tmp_error = 1;
+                  endcase // case (address)
+                end // if (core_ready)
             end // if (we)
 
           else
             begin
-              if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST15))
-                tmp_read_data = digest_reg[(15 - (address - ADDR_DIGEST0)) * 32 +: 32];
+              if (core_ready)
+                if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST15))
+                  tmp_read_data = digest_reg[(15 - (address - ADDR_DIGEST0)) * 32 +: 32];
 
               if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK31))
                 tmp_read_data = block_reg[address[4 : 0]];
@@ -420,9 +422,7 @@ module sha512(
                   tmp_read_data = work_factor_num_reg;
 
                 default:
-                  begin
-                    tmp_error = 1;
-                  end
+                  tmp_error = 1;
               endcase // case (address)
             end
         end

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