[Cryptech-Commits] [user/shatov/curve25519_fpga_model] branch master updated (f6636a2 -> 71bc54c)

git at cryptech.is git at cryptech.is
Mon Oct 15 13:17:09 UTC 2018

This is an automated email from the git hooks/post-receive script.

meisterpaul1 at yandex.ru pushed a change to branch master
in repository user/shatov/curve25519_fpga_model.

    from f6636a2  Added readme file (unfinished, will update after Verilog for Ed25519 is done)
     new 266984f  Reworked Ed25519-specific microcode, added magic markers to allow automatic parsing.
     new d62b3ee  Tiny cleanup.
     new 6f318dc  Removed move2(), because Verilog can only move one operand a time. Added magic markers to allow automatic parsing.
     new 71bc54c  Ed25519 microcode parser. Verilog Ed25519 core is microsequenced, it contains a "worker" module that fetches opcodes from a piece of read-only memory and does either "move" (copy) or "math" (add/subtract/multiply) operation. The C model mimics how this worker unit operates by calling routines that correspond to micro-operations. This parser processes the C model sources and generates a piece of Verilog that is used to initialize the microcode ROM.

The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "add" were already present in the repository and have only
been added to this reference.

Summary of changes:
 curve25519/curve25519_fpga_microcode.cpp | 105 +++---
 curve25519/curve25519_fpga_microcode.h   |   4 -
 curve25519/curve25519_fpga_modular.cpp   |   5 +-
 ed25519/ed25519_fpga_curve_microcode.cpp | 164 +++++----
 ed25519/ed25519_microcode_parser.py      | 566 +++++++++++++++++++++++++++++++
 5 files changed, 725 insertions(+), 119 deletions(-)
 create mode 100644 ed25519/ed25519_microcode_parser.py

More information about the Commits mailing list