[Cryptech-Commits] [core/platform/novena] 01/07: Merge branch 'activelow'
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Mon Nov 16 21:41:32 UTC 2015
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paul at psgd.org pushed a commit to branch master
in repository core/platform/novena.
commit 4cfd0c3dbe688960f6b7e7285b7a14cebb1586a3
Merge: c88137e 1eccd3c
Author: Paul Selkirk <paul at psgd.org>
Date: Thu Nov 12 15:41:48 2015 -0500
Merge branch 'activelow'
common/rtl/clkmgr_dcm.v | 7 +++++--
common/rtl/novena_clkmgr.v | 18 +++++++++++-------
2 files changed, 16 insertions(+), 9 deletions(-)
diff --cc common/rtl/clkmgr_dcm.v
index 5651b93,0000000..7c851f1
mode 100644,000000..100644
--- a/common/rtl/clkmgr_dcm.v
+++ b/common/rtl/clkmgr_dcm.v
@@@ -1,144 -1,0 +1,147 @@@
+//======================================================================
+//
+// clkmgr_dcm.v
+// ---------------
+// Xilinx DCM_SP primitive wrapper to avoid using Clocking Wizard IP core.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module clkmgr_dcm
+ (
+ input wire clk_in,
+ input wire reset_in,
+
+ output wire gclk_missing_out,
+
+ output wire clk_out,
+ output wire clk_valid_out
+ );
+
+
+ //
+ // Parameters
+ //
- parameter CLK_OUT_MUL = 2;
- parameter CLK_OUT_DIV = 2;
++ parameter CLK_OUT_MUL = 2; // multiply factor for output clock frequency (2..32)
++ parameter CLK_OUT_DIV = 2; // divide factor for output clock frequency (1..32)
+
+
+ //
+ // DCM_SP
+ //
++ /* Xilinx-specific primitive. */
+ wire dcm_clk_0;
+ wire dcm_clk_feedback;
+ wire dcm_clk_fx;
+ wire dcm_locked_int;
+ wire [ 7: 0] dcm_status_int;
+
+ DCM_SP #
+ (
+ .STARTUP_WAIT ("FALSE"),
+ .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
+ .CLK_FEEDBACK ("1X"),
+
+ .PHASE_SHIFT (0),
+ .CLKOUT_PHASE_SHIFT ("NONE"),
+
+ .CLKIN_PERIOD (20.0), // 50 MHz => 20 ns
+ .CLKIN_DIVIDE_BY_2 ("FALSE"),
+
+ .CLKDV_DIVIDE (5.000),
+ .CLKFX_MULTIPLY (CLK_OUT_MUL),
+ .CLKFX_DIVIDE (CLK_OUT_DIV)
+ )
+ DCM_SP_inst
+ (
+ .RST (reset_in),
+
+ .CLKIN (clk_in),
+ .CLKFB (dcm_clk_feedback),
+ .CLKDV (),
+
+ .CLK0 (dcm_clk_0),
+ .CLK90 (),
+ .CLK180 (),
+ .CLK270 (),
+
+ .CLK2X (),
+ .CLK2X180 (),
+
+ .CLKFX (dcm_clk_fx),
+ .CLKFX180 (),
+
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (),
+
+ .LOCKED (dcm_locked_int),
+ .STATUS (dcm_status_int),
+
+ .DSSEN (1'b0)
+ );
+
+
+ //
+ // Mapping
+ //
+ assign gclk_missing_out= dcm_status_int[1];
+ assign clk_valid_out = dcm_locked_int & ((dcm_status_int[2:1] == 2'b00) ? 1'b1 : 1'b0);
+
+
+ //
+ // Feedback
+ //
++ /* DCM_SP requires BUFG primitive in its feedback path. */
+ BUFG BUFG_feedback
+ (
+ .I (dcm_clk_0),
+ .O (dcm_clk_feedback)
+ );
+
+ //
+ // Output Buffer
+ //
++ /* Connect system clock to global clocking network. */
+ BUFG BUFG_output
+ (
+ .I (dcm_clk_fx),
+ .O (clk_out)
+ );
+
+
+endmodule
+
+//======================================================================
+// EOF clkmgr_dcm.v
+//======================================================================
diff --cc common/rtl/novena_clkmgr.v
index 9151e93,38a89eb..e8ef1bd
--- a/common/rtl/novena_clkmgr.v
+++ b/common/rtl/novena_clkmgr.v
@@@ -39,13 -39,13 +39,13 @@@
module novena_clkmgr
(
- input wire gclk_p, // signal from clock pins
- input wire gclk_n, //
+ input wire gclk_p, // signal from clock pins
+ input wire gclk_n, //
- input wire reset_mcu_b, // cpu reset (async, active-low)
+ input wire reset_mcu_b, // cpu reset (async, active-low)
- output wire sys_clk, // buffered system clock output
- output wire sys_rst_n // system reset output (async set, sync clear, active-low)
+ output wire sys_clk, // buffered system clock output
- output wire sys_rst // system reset output (sync, active-high)
++ output wire sys_rst_n // system reset output (async set, sync clear, active-low)
);
@@@ -97,7 -83,8 +97,8 @@@
//
/* DCM should be reset on power-up, when input clock is stopped or when the
- * CPU gets reset.
+ * CPU gets reset. Note that DCM requires active-high reset, so the shift
- * register is preloaded with 1's and gradually filled with 0's.
++ * register is preloaded with 1's and gradually filled with 0's.
*/
reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register
@@@ -116,9 -103,12 +117,12 @@@
// System Reset Logic
//
- /* System reset is asserted for 16 cycles whenever DCM aquires lock. */
- /* System reset is asserted for 16 cycles whenever DCM aquires lock. Note that system
- * reset is active-low, so the shift register is preloaded with 0's and gradually filled
- * with 1's afterwards.
- */
++ /* System reset is asserted for 16 cycles whenever DCM aquires lock. Note
++ * that system reset is active-low, so the shift register is preloaded with
++ * 0's and gradually filled with 1's.
++ */
- reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register
+ reg [15: 0] sys_rst_shreg = {16{1'b0}}; // 16-bit shift register
always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked)
//
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