[Cryptech-Commits] [core/math/modexp] 02/02: Adding module parameters for generic operand size to modexp_core and top level localparams with explanation in modexp.v to control the core instantiation.

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joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.

commit 906b9f1a5dbe37be9ce09c54a93095c41baab42a
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Tue Jun 23 10:00:57 2015 +0200

    Adding module parameters for generic operand size to modexp_core and top level localparams with explanation in modexp.v to control the core instantiation.
---
 src/rtl/modexp.v      | 77 ++++++++++++++++++++++++++++-----------------------
 src/rtl/modexp_core.v |  3 +-
 2 files changed, 45 insertions(+), 35 deletions(-)

diff --git a/src/rtl/modexp.v b/src/rtl/modexp.v
index 4e9fc51..65f4058 100644
--- a/src/rtl/modexp.v
+++ b/src/rtl/modexp.v
@@ -72,6 +72,14 @@ module modexp(
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
+  // The operand width is the internal operand width in bits.
+  // The address width is the size of the address space used. This
+  // value must be balances with OPERAND_WIDTH to allow a total
+  // of 8192 bits of data. OPERAND_WIDTH * (ADDRESS_WIDTH ** 2)
+  // is the formula. Note that the API data with is always 32 bits.
+  localparam OPERAND_WIDTH         = 32;
+  localparam ADDRESS_WIDTH         = 8;
+
   localparam GENERAL_PREFIX        = 4'h0;
   localparam ADDR_NAME0            = 8'h00;
   localparam ADDR_NAME1            = 8'h01;
@@ -162,40 +170,41 @@ module modexp(
   //----------------------------------------------------------------
   // core instantiations.
   //----------------------------------------------------------------
-  modexp_core core_inst(
-                        .clk(clk),
-                        .reset_n(reset_n),
-
-                        .start(start_reg),
-                        .ready(ready),
-
-                        .exponent_length(exponent_length_reg),
-                        .modulus_length(modulus_length_reg),
-
-                        .cycles(cycles),
-
-                        .exponent_mem_api_cs(exponent_mem_api_cs),
-                        .exponent_mem_api_wr(exponent_mem_api_wr),
-                        .exponent_mem_api_rst(exponent_mem_api_rst),
-                        .exponent_mem_api_write_data(write_data),
-                        .exponent_mem_api_read_data(exponent_mem_api_read_data),
-
-                        .modulus_mem_api_cs(modulus_mem_api_cs),
-                        .modulus_mem_api_wr(modulus_mem_api_wr),
-                        .modulus_mem_api_rst(modulus_mem_api_rst),
-                        .modulus_mem_api_write_data(write_data),
-                        .modulus_mem_api_read_data(modulus_mem_api_read_data),
-
-                        .message_mem_api_cs(message_mem_api_cs),
-                        .message_mem_api_wr(message_mem_api_wr),
-                        .message_mem_api_rst(message_mem_api_rst),
-                        .message_mem_api_write_data(write_data),
-                        .message_mem_api_read_data(message_mem_api_read_data),
-
-                        .result_mem_api_cs(result_mem_api_cs),
-                        .result_mem_api_rst(result_mem_api_rst),
-                        .result_mem_api_read_data(result_mem_api_read_data)
-                       );
+  modexp_core #(.OPW(OPERAND_WIDTH), .ADW(ADDRESS_WIDTH))
+  core_inst(
+            .clk(clk),
+            .reset_n(reset_n),
+
+            .start(start_reg),
+            .ready(ready),
+
+            .exponent_length(exponent_length_reg),
+            .modulus_length(modulus_length_reg),
+
+            .cycles(cycles),
+
+            .exponent_mem_api_cs(exponent_mem_api_cs),
+            .exponent_mem_api_wr(exponent_mem_api_wr),
+            .exponent_mem_api_rst(exponent_mem_api_rst),
+            .exponent_mem_api_write_data(write_data),
+            .exponent_mem_api_read_data(exponent_mem_api_read_data),
+
+            .modulus_mem_api_cs(modulus_mem_api_cs),
+            .modulus_mem_api_wr(modulus_mem_api_wr),
+            .modulus_mem_api_rst(modulus_mem_api_rst),
+            .modulus_mem_api_write_data(write_data),
+            .modulus_mem_api_read_data(modulus_mem_api_read_data),
+
+            .message_mem_api_cs(message_mem_api_cs),
+            .message_mem_api_wr(message_mem_api_wr),
+            .message_mem_api_rst(message_mem_api_rst),
+            .message_mem_api_write_data(write_data),
+            .message_mem_api_read_data(message_mem_api_read_data),
+
+            .result_mem_api_cs(result_mem_api_cs),
+            .result_mem_api_rst(result_mem_api_rst),
+            .result_mem_api_read_data(result_mem_api_read_data)
+           );
 
 
   //----------------------------------------------------------------
diff --git a/src/rtl/modexp_core.v b/src/rtl/modexp_core.v
index b8c4403..aa8a758 100644
--- a/src/rtl/modexp_core.v
+++ b/src/rtl/modexp_core.v
@@ -54,7 +54,8 @@
 //
 //======================================================================
 
-module modexp_core(
+module modexp_core #(parameter OPW = 32, parameter ADW = 8)
+                  (
                    input wire           clk,
                    input wire           reset_n,