[Cryptech-Commits] [core/math/modexp] 04/05: Fixed prev reg:

[git at cryptech.is]

This is an automated email from the git hooks/post-receive script.

joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.

commit f4fc1641d63a24f1e78b48361e951bc4e1e2b154
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Mon Jun 15 17:45:17 2015 +0200

    Fixed prev reg:
---
 src/rtl/montprod.v | 60 +++++++++++++++++++++++++++---------------------------
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 2c27941..de5e4c0 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -127,9 +127,9 @@ module montprod(
   reg [04 : 0] B_bit_index; //loop counter as a bit index
   reg [04 : 0] B_bit_index_reg; //loop counter as a bit index
 
-  reg [07 : 0] word_index; //register of what word is being read
+  reg [07 : 0] word_index_reg; //register of what word is being read
   reg [07 : 0] word_index_new; //calculation of what word to be read
-  reg [07 : 0] word_index_prev; //register of what word was read previously (result address to emit)
+  reg [07 : 0] word_index_prev_reg; //register of what word was read previously (result address to emit)
   reg [07 : 0] length_m1;
 
   reg          add_carry_in_sa;
@@ -219,28 +219,28 @@ module montprod(
     begin : reg_update
       if (!reset_n)
         begin
-          ready_reg         <= 1'b0;
-          loop_counter_reg  <= 13'h0;
-          word_index        <= 8'h0;
-          word_index_prev   <= 8'h0;
-          add_carry_in_sa   <= 1'b0;
-          add_carry_in_sm   <= 1'b0;
-          shr_carry_in      <= 1'b0;
-          montprod_ctrl_reg <= CTRL_IDLE;
-          b_reg             <= 1'b0;
-          q_reg             <= 1'b0;
-          s_mux_reg         <= SMUX_0;
-          s_mem_we_reg      <= 1'b0;
-          s_mem_wr_addr_reg <= 8'h0;
-          B_bit_index_reg   <= 5'h0;
+          ready_reg           <= 1'b0;
+          loop_counter_reg    <= 13'h0;
+          word_index_reg      <= 8'h0;
+          word_index_prev_reg <= 8'h0;
+          add_carry_in_sa     <= 1'b0;
+          add_carry_in_sm     <= 1'b0;
+          shr_carry_in        <= 1'b0;
+          b_reg               <= 1'b0;
+          q_reg               <= 1'b0;
+          s_mux_reg           <= SMUX_0;
+          s_mem_we_reg        <= 1'b0;
+          s_mem_wr_addr_reg   <= 8'h0;
+          B_bit_index_reg     <= 5'h0;
+          montprod_ctrl_reg   <= CTRL_IDLE;
         end
       else
         begin
           s_mem_wr_addr_reg <= s_mem_addr;
           s_mem_we_reg      <= s_mem_we_new;
 
-          word_index      <= word_index_new;
-          word_index_prev <= word_index;
+          word_index_reg      <= word_index_new;
+          word_index_prev_reg <= word_index_reg;
 
           shr_carry_in    <= shr_carry_new;
           add_carry_in_sa <= add_carry_new_sa;
@@ -361,21 +361,21 @@ module montprod(
           opa_addr_reg = length_m1;
 
         default:
-          opa_addr_reg = word_index;
+          opa_addr_reg = word_index_reg;
        endcase
 
        opb_addr_reg = B_word_index;
-       opm_addr_reg = word_index;
+       opm_addr_reg = word_index_reg;
 
       case (montprod_ctrl_reg)
         CTRL_LOOP_ITER:
           s_mem_addr = length_m1;
         default:
-          s_mem_addr = word_index;
+          s_mem_addr = word_index_reg;
       endcase
 
 
-      result_addr_reg  = word_index_prev;
+      result_addr_reg  = word_index_prev_reg;
       result_data_reg  = s_mem_read_data;
 
 
@@ -392,9 +392,9 @@ module montprod(
       else if (reset_word_index_MSW == 1'b1)
         word_index_new = 8'h0;
       else if (montprod_ctrl_reg == CTRL_L_CALC_SDIV2)
-        word_index_new = word_index + 1'b1;
+        word_index_new = word_index_reg + 1'b1;
       else
-        word_index_new = word_index - 1'b1;
+        word_index_new = word_index_reg - 1'b1;
     end // prodcalc
 
 
@@ -495,7 +495,7 @@ module montprod(
 
         CTRL_INIT_S:
           begin
-            if (word_index == 8'h0)
+            if (word_index_reg == 8'h0)
               begin
                  montprod_ctrl_new = CTRL_LOOP_INIT;
                  montprod_ctrl_we = 1'b1;
@@ -527,7 +527,7 @@ module montprod(
 
         CTRL_L_CALC_SM:
           begin
-            if (word_index == 8'h0)
+            if (word_index_reg == 8'h0)
               begin
                 reset_word_index_LSW = 1'b1;
                 montprod_ctrl_we     = 1'b1;
@@ -544,7 +544,7 @@ module montprod(
 
         CTRL_L_CALC_SA:
           begin
-            if (word_index == 8'h0)
+            if (word_index_reg == 8'h0)
               begin
                 reset_word_index_LSW = 1'b1;
                 montprod_ctrl_new    = CTRL_L_STALLPIPE_SA;
@@ -561,7 +561,7 @@ module montprod(
 
         CTRL_L_CALC_SDIV2:
           begin
-            if (word_index == length_m1)
+            if (word_index_reg == length_m1)
               begin
                 montprod_ctrl_new = CTRL_L_STALLPIPE_D2;
                 montprod_ctrl_we  = 1'b1;
@@ -590,8 +590,8 @@ module montprod(
         CTRL_EMIT_S:
            begin
              if (DEBUG)
-               $display("EMIT_S word_index: %d", word_index);
-             if (word_index_prev == 8'h0)
+               $display("EMIT_S word_index_reg: %d", word_index_reg);
+             if (word_index_prev_reg == 8'h0)
                begin
                  montprod_ctrl_new = CTRL_DONE;
                  montprod_ctrl_we  = 1'b1;