[Cryptech-Commits] [core/math/modexp] 03/05: (1) Fixing up write address register fo s mem. (2) Cleanup of loop counter.

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joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.

commit 1ba71b2fbee8e60b6fb788c95687b1921add774b
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Mon Jun 15 17:37:48 2015 +0200

    (1) Fixing up write address register fo s mem. (2) Cleanup of loop counter.
---
 src/rtl/montprod.v | 73 ++++++++++++++++++++++++++++++------------------------
 1 file changed, 41 insertions(+), 32 deletions(-)

diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 85eea11..2c27941 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -111,7 +111,7 @@ module montprod(
   reg           s_mem_we_reg;
   reg           s_mem_we_new;
   reg [07 : 0]  s_mem_addr;
-  reg [07 : 0]  s_mem_wr_addr;
+  reg [07 : 0]  s_mem_wr_addr_reg;
   wire [31 : 0] s_mem_read_data;
 
   reg           q; //q = (s - b * A) & 1
@@ -119,9 +119,9 @@ module montprod(
   reg           b; //b: bit of B
   reg           b_reg;
 
-  reg [12 : 0] loop_counter;
+  reg [12 : 0] loop_counter_reg;
   reg [12 : 0] loop_counter_new;
-  reg [12 : 0] loop_counter_dec;
+  reg          loop_counter_we;
 
   reg [07 : 0] B_word_index; //loop counter as a word index
   reg [04 : 0] B_bit_index; //loop counter as a bit index
@@ -179,7 +179,7 @@ module montprod(
                      .read_addr(s_mem_addr),
                      .read_data(s_mem_read_data),
                      .wr(s_mem_we_reg),
-                     .write_addr(s_mem_wr_addr),
+                     .write_addr(s_mem_wr_addr_reg),
                      .write_data(s_mem_new)
                     );
 
@@ -220,7 +220,7 @@ module montprod(
       if (!reset_n)
         begin
           ready_reg         <= 1'b0;
-          loop_counter      <= 13'h0;
+          loop_counter_reg  <= 13'h0;
           word_index        <= 8'h0;
           word_index_prev   <= 8'h0;
           add_carry_in_sa   <= 1'b0;
@@ -231,28 +231,18 @@ module montprod(
           q_reg             <= 1'b0;
           s_mux_reg         <= SMUX_0;
           s_mem_we_reg      <= 1'b0;
-          s_mem_wr_addr     <= 8'h0;
+          s_mem_wr_addr_reg <= 8'h0;
           B_bit_index_reg   <= 5'h0;
         end
       else
         begin
-          if (ready_we)
-            ready_reg <= ready_new;
-
-          if (montprod_ctrl_we)
-            begin
-               montprod_ctrl_reg <= montprod_ctrl_new;
-             end
-
-          s_mem_wr_addr <= s_mem_addr;
+          s_mem_wr_addr_reg <= s_mem_addr;
+          s_mem_we_reg      <= s_mem_we_new;
 
-          s_mem_we_reg <= s_mem_we_new;
-
-          word_index <= word_index_new;
+          word_index      <= word_index_new;
           word_index_prev <= word_index;
 
-          loop_counter <= loop_counter_new;
-          shr_carry_in <= shr_carry_new;
+          shr_carry_in    <= shr_carry_new;
           add_carry_in_sa <= add_carry_new_sa;
           add_carry_in_sm <= add_carry_new_sm;
 
@@ -261,7 +251,18 @@ module montprod(
           b_reg <= b;
 
           s_mux_reg <= s_mux_new;
-      end
+
+          if (ready_we)
+            ready_reg <= ready_new;
+
+          if (montprod_ctrl_we)
+            begin
+               montprod_ctrl_reg <= montprod_ctrl_new;
+             end
+
+          if (loop_counter_we)
+            loop_counter_reg <= loop_counter_new;
+        end
     end // reg_update
 
 
@@ -315,27 +316,35 @@ module montprod(
   always @*
     begin : loop_counter_logic
 
-      loop_counter_new  = loop_counter;
+      loop_counter_new = 13'h000;
+      loop_counter_we  = 1'b0;
+
       length_m1        = length - 1'b1;
-      loop_counter_dec = loop_counter - 1'b1;
-      B_word_index     = loop_counter[12:5];
+      B_word_index     = loop_counter_reg[12:5];
       B_bit_index      = B_bit_index_reg;
 
       case (montprod_ctrl_reg)
         CTRL_LOOP_INIT:
-          loop_counter_new = {length, 5'b00000} - 1'b1;
+          begin
+            loop_counter_new = {length, 5'b00000} - 1'b1;
+            loop_counter_we  = 1'b1;
+          end
 
         CTRL_LOOP_ITER:
           begin
-            B_word_index = loop_counter[12:5];
-            B_bit_index  = 5'h1f - loop_counter[4:0];
+            B_word_index = loop_counter_reg[12:5];
+            B_bit_index  = 5'h1f - loop_counter_reg[4:0];
           end
 
         CTRL_L_STALLPIPE_D2:
-          loop_counter_new = loop_counter_dec;
+          begin
+            loop_counter_new = loop_counter_reg - 1'b1;
+            loop_counter_we  = 1'b1;
+          end
 
         default:
-          loop_counter_new = loop_counter;
+          begin
+          end
       endcase
     end
 
@@ -366,11 +375,10 @@ module montprod(
       endcase
 
 
-
-
       result_addr_reg  = word_index_prev;
       result_data_reg  = s_mem_read_data;
 
+
       case (montprod_ctrl_reg)
         CTRL_EMIT_S:
            tmp_result_we = 1'b1;
@@ -565,7 +573,8 @@ module montprod(
             montprod_ctrl_new    = CTRL_LOOP_ITER; //loop
             montprod_ctrl_we     = 1'b1;
             reset_word_index_LSW = 1'b1;
-            if (loop_counter == 0)
+
+            if (loop_counter_reg == 0)
               begin
                 montprod_ctrl_new = CTRL_L_STALLPIPE_ES;
                 montprod_ctrl_we  = 1'b1;