[Cryptech-Commits] [user/js/test/novena_eim_base] 02/02: Moved sync reset up to a common macro dir.

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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.

commit b7f491c0e603af1f2e8ae27eeefd6aa47ff576c9
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Thu Jan 22 10:53:06 2015 +0100

    Moved sync reset up to a common macro dir.
---
 src/macros/clk_dll.v                     | 158 +++++++++++++++++++++++++++++++
 src/macros/{sync_reset => }/sync_reset.v |   0
 2 files changed, 158 insertions(+)

diff --git a/src/macros/clk_dll.v b/src/macros/clk_dll.v
new file mode 100644
index 0000000..74e30a3
--- /dev/null
+++ b/src/macros/clk_dll.v
@@ -0,0 +1,158 @@
+// file: clk_dll.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1____50.000______0.000______50.0______267.325____251.827
+// CLK_OUT2____25.000______0.000______50.0______308.718____251.827
+// CLK_OUT3_____3.200______0.000______50.0______464.696____251.827
+//
+//----------------------------------------------------------------------------
+// "Input Clock   Freq (MHz)    Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary______________50____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clk_dll,clk_wiz_v3_6,{component_name=clk_dll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,ma [...]
+module clk_dll
+ (// Clock in ports
+  input         clk50in,
+  // Clock out ports
+  output        clk50,
+  output        clk25,
+  output        clk3p2,
+  // Status and control signals
+  input         RESET,
+  output        LOCKED
+ );
+
+  // Input buffering
+  //------------------------------------
+  BUFG clkin1_buf
+   (.O (clkin1),
+    .I (clk50in));
+
+
+  // Clocking primitive
+  //------------------------------------
+  // Instantiation of the PLL primitive
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+  wire [15:0] do_unused;
+  wire        drdy_unused;
+  wire        clkfbout;
+  wire        clkfbout_buf;
+  wire        clkout3_unused;
+  wire        clkout4_unused;
+  wire        clkout5_unused;
+
+  PLL_BASE
+  #(.BANDWIDTH              ("OPTIMIZED"),
+    .CLK_FEEDBACK           ("CLKFBOUT"),
+    .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
+    .DIVCLK_DIVIDE          (1),
+    .CLKFBOUT_MULT          (8),
+    .CLKFBOUT_PHASE         (0.000),
+    .CLKOUT0_DIVIDE         (8),
+    .CLKOUT0_PHASE          (0.000),
+    .CLKOUT0_DUTY_CYCLE     (0.500),
+    .CLKOUT1_DIVIDE         (16),
+    .CLKOUT1_PHASE          (0.000),
+    .CLKOUT1_DUTY_CYCLE     (0.500),
+    .CLKOUT2_DIVIDE         (125),
+    .CLKOUT2_PHASE          (0.000),
+    .CLKOUT2_DUTY_CYCLE     (0.500),
+    .CLKIN_PERIOD           (20.0),
+    .REF_JITTER             (0.010))
+  pll_base_inst
+    // Output clocks
+   (.CLKFBOUT              (clkfbout),
+    .CLKOUT0               (clkout0),
+    .CLKOUT1               (clkout1),
+    .CLKOUT2               (clkout2),
+    .CLKOUT3               (clkout3_unused),
+    .CLKOUT4               (clkout4_unused),
+    .CLKOUT5               (clkout5_unused),
+    // Status and control signals
+    .LOCKED                (LOCKED),
+    .RST                   (RESET),
+     // Input clock control
+    .CLKFBIN               (clkfbout_buf),
+    .CLKIN                 (clkin1));
+
+
+  // Output buffering
+  //-----------------------------------
+  BUFG clkf_buf
+   (.O (clkfbout_buf),
+    .I (clkfbout));
+
+  BUFG clkout1_buf
+   (.O   (clk50),
+    .I   (clkout0));
+
+
+  BUFG clkout2_buf
+   (.O   (clk25),
+    .I   (clkout1));
+
+  BUFG clkout3_buf
+   (.O   (clk3p2),
+    .I   (clkout2));
+
+
+
+endmodule
diff --git a/src/macros/sync_reset/sync_reset.v b/src/macros/sync_reset.v
similarity index 100%
rename from src/macros/sync_reset/sync_reset.v
rename to src/macros/sync_reset.v