[Cryptech-Commits] [user/js/test/novena_eim_base] 01/02: Fixed names of wires connected to clocks. Added new clock ports.

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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.

commit ef66b7f7dd20c4909a1a7a892b60115a7274f56a
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Thu Jan 22 10:44:23 2015 +0100

    Fixed names of wires connected to clocks. Added new clock ports.
---
 src/rtl/novena_fpga.v | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v
index ea73c04..a73bc28 100644
--- a/src/rtl/novena_fpga.v
+++ b/src/rtl/novena_fpga.v
@@ -68,10 +68,12 @@ module novena_fpga(
   wire reset;
 
   wire clk50;
+  wire clk25;
+  wire clk3_2;
 
-  wire bclk;
-  wire bclk_i;
-  wire bclk_o;
+  wire bclk133;
+  wire bclk133_i;
+  wire bclk133_o;
 
 
   //----------------------------------------------------------------
@@ -108,10 +110,12 @@ module novena_fpga(
                              .reset(reset),
 
                              .clk50(clk50),
+                             .clk25(clk25),
+                             .clk3_2(clk3_2),
 
-                             .eim_bclk(bclk),
-                             .eim_bclk_i(bclk_i),
-                             .eim_bclk_o(bclk_o)
+                             .eim_bclk(bclk133),
+                             .eim_bclk_i(bclk133_i),
+                             .eim_bclk_o(bclk133_o)
 	                    );