[Cryptech-Commits] [user/js/test/novena_eim_base] 01/02: (1) Updated clock interface with new eim clock names. (2) Commented out everything except the heartbeat functionality.
git at cryptech.is
git at cryptech.is
Wed Jan 21 12:46:24 UTC 2015
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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.
commit 6b2372c9f7d16851195363f6e7f5b4dc3c9c4966
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Wed Jan 21 13:44:38 2015 +0100
(1) Updated clock interface with new eim clock names. (2) Commented out everything except the heartbeat functionality.
---
src/rtl/novena_fpga.v | 735 ++++++++++++++++++++++++++------------------------
1 file changed, 378 insertions(+), 357 deletions(-)
diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v
index ce8dfcd..593a9a1 100755
--- a/src/rtl/novena_fpga.v
+++ b/src/rtl/novena_fpga.v
@@ -56,13 +56,20 @@ module novena_fpga(
//----------------------------------------------------------------
- // Internal constant and parameter definitions.
+ // Registers.
//----------------------------------------------------------------
//----------------------------------------------------------------
- // Registers including update variables and write enable.
+ // Wires.
//----------------------------------------------------------------
+ wire reset;
+
+ wire clk50;
+
+ wire bclk;
+ wire bclk_i;
+ wire bclk_o;
//----------------------------------------------------------------
@@ -86,251 +93,22 @@ module novena_fpga(
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
-o
-
- //----------------------------------------------------------------
- // Wires.
- //----------------------------------------------------------------
- wire [15:0] eim_dout;
- wire [15:0] eim_din;
- wire clk; // free-runs at 50 MHz, unbuffered
- wire clk50; // zero-delay, DLL version of above. Use this.
- wire clk100; // doubled-up version of the above. For time base applications.
- wire bclk; // NOTE: doesn't run until first CPU access to EIM; then free-runs at 133 MHz
- reg [23:0] counter;
-
- wire ddr3_dll_locked;
- wire ddr3clk;
-
-
- wire reset;
- reg emulate_r;
-
- always @(posedge spiclk) begin
- emulate_r <= emulate;
- end
-
-
- // P15 is cs output to SPINOR
-// assign F_LVDS_P15 = F_DX18; // set this for bypass mode
-// assign F_LVDS_P15 = 1'b1; // set to 1 to disable SPINOR during emulation
-
-
- ////////////////////////////////////
- ///// MASTER RESET
- ////////////////////////////////////
-
- sync_reset master_res_sync( .glbl_reset(!RESETBMCU), .clk(clk), .reset(reset) );
-
- wire bclk_dll, bclk_div2_dll, bclk_div4_dll, bclk_locked;
- wire bclk_early;
-
- ////////////////////////////////////
- ///// BCLK DLL -- generate zero-delay clock plus slower versions for internal use
- ////////////////////////////////////
- wire bclk_int_in, bclk_io_in;
- IBUFG clkibufg (.I(EIM_BCLK), .O(bclk) );
- BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in) );
-
- bclk_dll bclk_dll_mod( .clk133in(bclk_int_in), .clk133(bclk_dll),
- .RESET(reset), .LOCKED(bclk_locked));
-
- wire i_reset, i_locked;
- wire o_reset, o_locked;
- wire bclk_i, bclk_o;
- wire i_fbk_out, i_fbk_in;
- wire o_fbk_out, o_fbk_in;
-
- dcm_delay bclk_i_dll( .clk133(bclk_int_in), .clk133out(bclk_i),
- .CLKFB_IN(i_fbk_in), .CLKFB_OUT(i_fbk_out),
- .RESET(i_reset), .LOCKED(i_locked));
-
- dcm_delay bclk_o_dll( .clk133(bclk_int_in), .clk133out(bclk_o),
- .CLKFB_IN(o_fbk_in), .CLKFB_OUT(o_fbk_out),
- .RESET(o_reset), .LOCKED(o_locked));
-
- // lock it to the input path
- BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in));
- // assign o_fbk_in = bclk_o;
-// BUFG bclk_io_fbk(.I(bclk_io), .O(io_fbk_in));
-
- assign i_fbk_in = bclk_i;
-
- ////////////////////////////////////
- ///// Register set -- area-inefficient, high fan-out/in registers for controlling/monitoring internal signals
- ///// All registers split into write or read only blanks
- ///// 0x40000 - 0x40FFF is reserved for w/o
- ///// 0x41000 - 0x41FFF is reserved for r/o
- ///// -> if you want to check a w/o value, loop it back to an r/o register
- ////////////////////////////////////
-
- reg cs0_r, rw_r;
- reg [15:0] din_r;
- reg [18:0] bus_addr_r;
- reg adv_r;
-
- reg cs0_in, rw_in, adv_in;
- reg [15:0] din_in;
- reg [2:0] a_in;
-
- always @(posedge bclk_i) begin
- cs0_in <= EIM_CS[0];
- rw_in <= EIM_RW;
- din_in <= eim_din;
- adv_in <= !EIM_LBA; // latch address on LBA low
- a_in <= EIM_A[18:16];
-
- cs0_r <= cs0_in;
- rw_r <= rw_in;
- din_r <= din_in;
- adv_r <= adv_in;
- end
-
- always @(posedge bclk_i) begin
- if( adv_in ) begin
- bus_addr_r <= {a_in, din_in};
- end else begin
- bus_addr_r <= bus_addr_r;
- end
- end
+ novena_fpga_clocks clk_rst(
+ .RESETBMCU(RESETBMCU),
- wire [15:0] r40000wo;
- wire [15:0] r40002wo;
+ .CLK2_N(CLK2_N),
+ .CLK2_P(CLK2_P),
- wire [15:0] ro_d;
+ .EIM_BCLK(EIM_BCLK),
- //////// write-only registers
- reg_wo reg_wo_40000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40000),
- .bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
- .reg_d( r40000wo[15:0] ) );
+ .reset(reset),
- reg_wo reg_wo_40002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40002),
- .bus_d(din_r), .we(!cs0_r && !rw_r), .re(1'b0), .rbk_d(ro_d), // unreadable
- .reg_d( r40002wo[15:0] ) );
+ .clk50(clk50),
-
- reg_wo reg_wo_40010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40010),
- .bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r),
- .rbk_d(ro_d), .reg_d( romulator_ctl[15:0] ) );
-
-
- //////// read-only registers
- // loopback readback
- reg_ro reg_ro_41000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41000),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( r40000wo[15:0] ) );
-
- reg_ro reg_ro_41002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41002),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( r40002wo[15:0] ) );
-
-
- wire [15:0] romulator_stat;
- reg_ro reg_ro_41100 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41100),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_stat[15:0] ) );
-
- wire [15:0] romulator_count;
- reg_ro reg_ro_41102 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41102),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_count[15:0] ) );
-
- wire [15:0] romulator_adr_stat;
- reg_ro reg_ro_41104 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41104),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_adr_stat[15:0] ) );
-
- wire [15:0] romulator_adr_count;
- reg_ro reg_ro_41106 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41106),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_adr_count[15:0] ) );
-
- wire [23:0] romulator_adr_dout;
- reg_ro reg_ro_41108 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41108),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_adr_dout[15:0] ) );
-
- reg_ro reg_ro_4110A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110A),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( {8'b0,romulator_adr_dout[23:16]} ) );
-
- wire [15:0] romulator_out_stat;
- reg_ro reg_ro_4110C ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110C),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_out_stat[15:0] ) );
-
- wire [15:0] romulator_out_count;
- reg_ro reg_ro_4110E ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110E),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_out_count[15:0] ) );
-
- ///////////////////////
- ///////////////////////
- // CS1 bank registers: minimum size here is 64-bit, tuned for synchronous burst access only
- ///////////////////////
-
- wire [63:0] rC04_0000wo;
- wire [63:0] rC04_0008wo;
- wire [15:0] ro_d_b;
-
- ///////// write registers
- // loopback test
- reg_wo_4burst reg_wo_4b_C04_0000( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_0000),
- .bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
- .reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
-
- reg_wo_4burst reg_wo_4b_C04_0008( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_0008),
- .bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
- .reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
-
- ///////// read registers
- // loopback test
- reg_ro_4burst reg_ro_4b_C04_1000( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_1000),
- .bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
- .reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
-
- reg_ro_4burst reg_ro_4b_C04_1008( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_1008),
- .bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
- .reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
-
- // FPGA minor version code
- reg_ro reg_ro_41FFC ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFC),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( 16'h0001 ) ); // minor version
-
- // FPGA major version code
- reg_ro reg_ro_41FFE ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFE),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( 16'h000A ) ); // 000A is for the SPI romulator
-
- ////////// VERSION LOG (major version 000A) /////////////
- //////
- // Minor version 0001, May 13 2014
- // Initial cull to the SPI ROM feature set
- //
-
- // mux between block memory and register set based on high bits
- // assign eim_dout = (bus_addr[18:16] != 3'b000) ? ro_d : bram_dout;
- // pipeline to improve timing
- reg [15:0] ro_d_r;
- reg [15:0] ro_d_b_r;
- reg [1:0] eim_rdcs;
- reg [15:0] eim_dout_pipe;
- reg [15:0] eim_dout_pipe2;
-
- always @(posedge bclk_i) begin
- ro_d_b_r <= ro_d_b;
- end
-
- always @(posedge bclk_dll) begin
- ro_d_r <= ro_d;
- eim_rdcs[1:0] <= EIM_CS[1:0];
- eim_dout_pipe <= (eim_rdcs[1:0] == 2'b10) ? ro_d_r : ro_d_b_r;
- end
-
- always @(posedge bclk_o) begin
- eim_dout_pipe2 <= eim_dout_pipe; // retime near the source to allow max time for wire delay
- end;
+ .eim_bclk(bclk),
+ .eim_bclk_i(bclk_i),
+ .eim_bclk_o(bclk_o)
+ );
//----------------------------------------------------------------
@@ -344,124 +122,367 @@ o
assign FPGA_LED2 = counter[23];
- //----------------------------------------------------------------
- // EIM stuff to be moved.
- //----------------------------------------------------------------
- reg [15:0] eim_d_t;
- reg eim_lba_reg;
- reg eim_oe_reg;
-
- always @(posedge bclk_i) begin
- eim_lba_reg <= EIM_LBA;
- eim_oe_reg <= EIM_OE;
- end
-
- always @(posedge bclk_o) begin
- eim_d_t[ 0] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 1] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 2] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 3] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 4] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 5] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 6] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 7] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 8] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 9] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[10] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[11] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[12] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[13] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[14] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[15] = eim_oe_reg | !eim_lba_reg;
- end
-
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim0 (.IO(EIM_DA[ 0]), .I(eim_dout[ 0]), .T(eim_d_t), .O(eim_din[ 0]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim1 (.IO(EIM_DA[ 1]), .I(eim_dout[ 1]), .T(eim_d_t), .O(eim_din[ 1]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim2 (.IO(EIM_DA[ 2]), .I(eim_dout[ 2]), .T(eim_d_t), .O(eim_din[ 2]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim3 (.IO(EIM_DA[ 3]), .I(eim_dout[ 3]), .T(eim_d_t), .O(eim_din[ 3]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim4 (.IO(EIM_DA[ 4]), .I(eim_dout[ 4]), .T(eim_d_t), .O(eim_din[ 4]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim5 (.IO(EIM_DA[ 5]), .I(eim_dout[ 5]), .T(eim_d_t), .O(eim_din[ 5]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim6 (.IO(EIM_DA[ 6]), .I(eim_dout[ 6]), .T(eim_d_t), .O(eim_din[ 6]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim7 (.IO(EIM_DA[ 7]), .I(eim_dout[ 7]), .T(eim_d_t), .O(eim_din[ 7]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim8 (.IO(EIM_DA[ 8]), .I(eim_dout[ 8]), .T(eim_d_t), .O(eim_din[ 8]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim9 (.IO(EIM_DA[ 9]), .I(eim_dout[ 9]), .T(eim_d_t), .O(eim_din[ 9]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim10 (.IO(EIM_DA[10]), .I(eim_dout[10]), .T(eim_d_t), .O(eim_din[10]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim11 (.IO(EIM_DA[11]), .I(eim_dout[11]), .T(eim_d_t), .O(eim_din[11]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim12 (.IO(EIM_DA[12]), .I(eim_dout[12]), .T(eim_d_t), .O(eim_din[12]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim13 (.IO(EIM_DA[13]), .I(eim_dout[13]), .T(eim_d_t), .O(eim_din[13]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t), .O(eim_din[14]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t), .O(eim_din[15]));
-
- //////////////
- // Output pipeline registers -- explicit instantiation as their LOCs are controlled in the UCF.
- //////////////
- FDSE oddr2_eim0( .D( eim_dout_pipe2[0] ),
- .C( bclk_o ),
- .Q( eim_dout[0] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim1( .D( eim_dout_pipe2[1] ),
- .C( bclk_o ),
- .Q( eim_dout[1] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim2( .D( eim_dout_pipe2[2] ),
- .C( bclk_o ),
- .Q( eim_dout[2] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim3( .D( eim_dout_pipe2[3] ),
- .C( bclk_o ),
- .Q( eim_dout[3] ),
- .CE( 1'b1 ), .S(1'b0) );
+// wire [15:0] eim_dout;
+// wire [15:0] eim_din;
+// wire clk; // free-runs at 50 MHz, unbuffered
+// wire clk50; // zero-delay, DLL version of above. Use this.
+// wire clk100; // doubled-up version of the above. For time base applications.
+// wire bclk; // NOTE: doesn't run until first CPU access to EIM; then free-runs at 133 MHz
+// reg [23:0] counter;
+//
+// wire ddr3_dll_locked;
+// wire ddr3clk;
+//
+//
+// wire reset;
+// reg emulate_r;
+//
+// always @(posedge spiclk) begin
+// emulate_r <= emulate;
+// end
+//
+//
+// // P15 is cs output to SPINOR
+//// assign F_LVDS_P15 = F_DX18; // set this for bypass mode
+//// assign F_LVDS_P15 = 1'b1; // set to 1 to disable SPINOR during emulation
+//
+//
+// ////////////////////////////////////
+// ///// MASTER RESET
+// ////////////////////////////////////
+//
+// sync_reset master_res_sync( .glbl_reset(!RESETBMCU), .clk(clk), .reset(reset) );
+//
+// wire bclk_dll, bclk_div2_dll, bclk_div4_dll, bclk_locked;
+// wire bclk_early;
+//
+// ////////////////////////////////////
+// ///// BCLK DLL -- generate zero-delay clock plus slower versions for internal use
+// ////////////////////////////////////
+// wire bclk_int_in, bclk_io_in;
+// IBUFG clkibufg (.I(EIM_BCLK), .O(bclk) );
+// BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in) );
+//
+// bclk_dll bclk_dll_mod( .clk133in(bclk_int_in), .clk133(bclk_dll),
+// .RESET(reset), .LOCKED(bclk_locked));
+//
+// wire i_reset, i_locked;
+// wire o_reset, o_locked;
+// wire bclk_i, bclk_o;
+// wire i_fbk_out, i_fbk_in;
+// wire o_fbk_out, o_fbk_in;
+//
+// dcm_delay bclk_i_dll( .clk133(bclk_int_in), .clk133out(bclk_i),
+// .CLKFB_IN(i_fbk_in), .CLKFB_OUT(i_fbk_out),
+// .RESET(i_reset), .LOCKED(i_locked));
+//
+// dcm_delay bclk_o_dll( .clk133(bclk_int_in), .clk133out(bclk_o),
+// .CLKFB_IN(o_fbk_in), .CLKFB_OUT(o_fbk_out),
+// .RESET(o_reset), .LOCKED(o_locked));
+//
+// // lock it to the input path
+// BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in));
+// // assign o_fbk_in = bclk_o;
+//// BUFG bclk_io_fbk(.I(bclk_io), .O(io_fbk_in));
+//
+// assign i_fbk_in = bclk_i;
+//
+// ////////////////////////////////////
+// ///// Register set -- area-inefficient, high fan-out/in registers for controlling/monitoring internal signals
+// ///// All registers split into write or read only blanks
+// ///// 0x40000 - 0x40FFF is reserved for w/o
+// ///// 0x41000 - 0x41FFF is reserved for r/o
+// ///// -> if you want to check a w/o value, loop it back to an r/o register
+// ////////////////////////////////////
+//
+// reg cs0_r, rw_r;
+// reg [15:0] din_r;
+// reg [18:0] bus_addr_r;
+// reg adv_r;
+//
+// reg cs0_in, rw_in, adv_in;
+// reg [15:0] din_in;
+// reg [2:0] a_in;
+//
+// always @(posedge bclk_i) begin
+// cs0_in <= EIM_CS[0];
+// rw_in <= EIM_RW;
+// din_in <= eim_din;
+// adv_in <= !EIM_LBA; // latch address on LBA low
+// a_in <= EIM_A[18:16];
+//
+// cs0_r <= cs0_in;
+// rw_r <= rw_in;
+// din_r <= din_in;
+// adv_r <= adv_in;
+// end
+//
+// always @(posedge bclk_i) begin
+// if( adv_in ) begin
+// bus_addr_r <= {a_in, din_in};
+// end else begin
+// bus_addr_r <= bus_addr_r;
+// end
+// end
+//
+// wire [15:0] r40000wo;
+// wire [15:0] r40002wo;
+//
+// wire [15:0] ro_d;
+//
+// //////// write-only registers
+// reg_wo reg_wo_40000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40000),
+// .bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
+// .reg_d( r40000wo[15:0] ) );
+//
+// reg_wo reg_wo_40002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40002),
+// .bus_d(din_r), .we(!cs0_r && !rw_r), .re(1'b0), .rbk_d(ro_d), // unreadable
+// .reg_d( r40002wo[15:0] ) );
+//
+//
+// reg_wo reg_wo_40010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40010),
+// .bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r),
+// .rbk_d(ro_d), .reg_d( romulator_ctl[15:0] ) );
+//
+//
+// //////// read-only registers
+// // loopback readback
+// reg_ro reg_ro_41000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41000),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( r40000wo[15:0] ) );
+//
+// reg_ro reg_ro_41002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41002),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( r40002wo[15:0] ) );
+//
+//
+// wire [15:0] romulator_stat;
+// reg_ro reg_ro_41100 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41100),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( romulator_stat[15:0] ) );
+//
+// wire [15:0] romulator_count;
+// reg_ro reg_ro_41102 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41102),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( romulator_count[15:0] ) );
+//
+// wire [15:0] romulator_adr_stat;
+// reg_ro reg_ro_41104 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41104),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( romulator_adr_stat[15:0] ) );
+//
+// wire [15:0] romulator_adr_count;
+// reg_ro reg_ro_41106 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41106),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( romulator_adr_count[15:0] ) );
+//
+// wire [23:0] romulator_adr_dout;
+// reg_ro reg_ro_41108 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41108),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( romulator_adr_dout[15:0] ) );
+//
+// reg_ro reg_ro_4110A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110A),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( {8'b0,romulator_adr_dout[23:16]} ) );
+//
+// wire [15:0] romulator_out_stat;
+// reg_ro reg_ro_4110C ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110C),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( romulator_out_stat[15:0] ) );
+//
+// wire [15:0] romulator_out_count;
+// reg_ro reg_ro_4110E ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110E),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( romulator_out_count[15:0] ) );
+//
+// ///////////////////////
+// ///////////////////////
+// // CS1 bank registers: minimum size here is 64-bit, tuned for synchronous burst access only
+// ///////////////////////
+//
+// wire [63:0] rC04_0000wo;
+// wire [63:0] rC04_0008wo;
+// wire [15:0] ro_d_b;
+//
+// ///////// write registers
+// // loopback test
+// reg_wo_4burst reg_wo_4b_C04_0000( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_0000),
+// .bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
+// .reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
+//
+// reg_wo_4burst reg_wo_4b_C04_0008( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_0008),
+// .bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
+// .reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
+//
+// ///////// read registers
+// // loopback test
+// reg_ro_4burst reg_ro_4b_C04_1000( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_1000),
+// .bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
+// .reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
+//
+// reg_ro_4burst reg_ro_4b_C04_1008( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_1008),
+// .bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
+// .reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
+//
+// // FPGA minor version code
+// reg_ro reg_ro_41FFC ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFC),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( 16'h0001 ) ); // minor version
+//
+// // FPGA major version code
+// reg_ro reg_ro_41FFE ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFE),
+// .bus_d(ro_d), .re(!cs0_r && rw_r),
+// .reg_d( 16'h000A ) ); // 000A is for the SPI romulator
+//
+// ////////// VERSION LOG (major version 000A) /////////////
+// //////
+// // Minor version 0001, May 13 2014
+// // Initial cull to the SPI ROM feature set
+// //
+//
+// // mux between block memory and register set based on high bits
+// // assign eim_dout = (bus_addr[18:16] != 3'b000) ? ro_d : bram_dout;
+// // pipeline to improve timing
+// reg [15:0] ro_d_r;
+// reg [15:0] ro_d_b_r;
+// reg [1:0] eim_rdcs;
+// reg [15:0] eim_dout_pipe;
+// reg [15:0] eim_dout_pipe2;
+//
+// always @(posedge bclk_i) begin
+// ro_d_b_r <= ro_d_b;
+// end
+//
+// always @(posedge bclk_dll) begin
+// ro_d_r <= ro_d;
+// eim_rdcs[1:0] <= EIM_CS[1:0];
+// eim_dout_pipe <= (eim_rdcs[1:0] == 2'b10) ? ro_d_r : ro_d_b_r;
+// end
+//
+// always @(posedge bclk_o) begin
+// eim_dout_pipe2 <= eim_dout_pipe; // retime near the source to allow max time for wire delay
+// end;
- FDSE oddr2_eim4( .D( eim_dout_pipe2[4] ),
- .C( bclk_o ),
- .Q( eim_dout[4] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim5( .D( eim_dout_pipe2[5] ),
- .C( bclk_o ),
- .Q( eim_dout[5] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim6( .D( eim_dout_pipe2[6] ),
- .C( bclk_o ),
- .Q( eim_dout[6] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim7( .D( eim_dout_pipe2[7] ),
- .C( bclk_o ),
- .Q( eim_dout[7] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim8( .D( eim_dout_pipe2[8] ),
- .C( bclk_o ),
- .Q( eim_dout[8] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim9( .D( eim_dout_pipe2[9] ),
- .C( bclk_o ),
- .Q( eim_dout[9] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimA( .D( eim_dout_pipe2[10] ),
- .C( bclk_o ),
- .Q( eim_dout[10] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimB( .D( eim_dout_pipe2[11] ),
- .C( bclk_o ),
- .Q( eim_dout[11] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimC( .D( eim_dout_pipe2[12] ),
- .C( bclk_o ),
- .Q( eim_dout[12] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimD( .D( eim_dout_pipe2[13] ),
- .C( bclk_o ),
- .Q( eim_dout[13] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimE( .D( eim_dout_pipe2[14] ),
- .C( bclk_o ),
- .Q( eim_dout[14] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimF( .D( eim_dout_pipe2[15] ),
- .C( bclk_o ),
- .Q( eim_dout[15] ),
- .CE( 1'b1 ), .S(1'b0) );
+// //----------------------------------------------------------------
+// // EIM stuff to be moved.
+// //----------------------------------------------------------------
+// reg [15:0] eim_d_t;
+// reg eim_lba_reg;
+// reg eim_oe_reg;
+//
+// always @(posedge bclk_i) begin
+// eim_lba_reg <= EIM_LBA;
+// eim_oe_reg <= EIM_OE;
+// end
+//
+// always @(posedge bclk_o) begin
+// eim_d_t[ 0] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[ 1] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[ 2] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[ 3] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[ 4] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[ 5] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[ 6] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[ 7] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[ 8] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[ 9] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[10] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[11] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[12] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[13] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[14] = eim_oe_reg | !eim_lba_reg;
+// eim_d_t[15] = eim_oe_reg | !eim_lba_reg;
+// end
+//
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim0 (.IO(EIM_DA[ 0]), .I(eim_dout[ 0]), .T(eim_d_t), .O(eim_din[ 0]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim1 (.IO(EIM_DA[ 1]), .I(eim_dout[ 1]), .T(eim_d_t), .O(eim_din[ 1]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim2 (.IO(EIM_DA[ 2]), .I(eim_dout[ 2]), .T(eim_d_t), .O(eim_din[ 2]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim3 (.IO(EIM_DA[ 3]), .I(eim_dout[ 3]), .T(eim_d_t), .O(eim_din[ 3]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim4 (.IO(EIM_DA[ 4]), .I(eim_dout[ 4]), .T(eim_d_t), .O(eim_din[ 4]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim5 (.IO(EIM_DA[ 5]), .I(eim_dout[ 5]), .T(eim_d_t), .O(eim_din[ 5]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim6 (.IO(EIM_DA[ 6]), .I(eim_dout[ 6]), .T(eim_d_t), .O(eim_din[ 6]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim7 (.IO(EIM_DA[ 7]), .I(eim_dout[ 7]), .T(eim_d_t), .O(eim_din[ 7]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim8 (.IO(EIM_DA[ 8]), .I(eim_dout[ 8]), .T(eim_d_t), .O(eim_din[ 8]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim9 (.IO(EIM_DA[ 9]), .I(eim_dout[ 9]), .T(eim_d_t), .O(eim_din[ 9]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim10 (.IO(EIM_DA[10]), .I(eim_dout[10]), .T(eim_d_t), .O(eim_din[10]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim11 (.IO(EIM_DA[11]), .I(eim_dout[11]), .T(eim_d_t), .O(eim_din[11]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim12 (.IO(EIM_DA[12]), .I(eim_dout[12]), .T(eim_d_t), .O(eim_din[12]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim13 (.IO(EIM_DA[13]), .I(eim_dout[13]), .T(eim_d_t), .O(eim_din[13]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t), .O(eim_din[14]));
+// IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t), .O(eim_din[15]));
+//
+// //////////////
+// // Output pipeline registers -- explicit instantiation as their LOCs are controlled in the UCF.
+// //////////////
+// FDSE oddr2_eim0( .D( eim_dout_pipe2[0] ),
+// .C( bclk_o ),
+// .Q( eim_dout[0] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eim1( .D( eim_dout_pipe2[1] ),
+// .C( bclk_o ),
+// .Q( eim_dout[1] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eim2( .D( eim_dout_pipe2[2] ),
+// .C( bclk_o ),
+// .Q( eim_dout[2] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eim3( .D( eim_dout_pipe2[3] ),
+// .C( bclk_o ),
+// .Q( eim_dout[3] ),
+// .CE( 1'b1 ), .S(1'b0) );
+//
+// FDSE oddr2_eim4( .D( eim_dout_pipe2[4] ),
+// .C( bclk_o ),
+// .Q( eim_dout[4] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eim5( .D( eim_dout_pipe2[5] ),
+// .C( bclk_o ),
+// .Q( eim_dout[5] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eim6( .D( eim_dout_pipe2[6] ),
+// .C( bclk_o ),
+// .Q( eim_dout[6] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eim7( .D( eim_dout_pipe2[7] ),
+// .C( bclk_o ),
+// .Q( eim_dout[7] ),
+// .CE( 1'b1 ), .S(1'b0) );
+//
+// FDSE oddr2_eim8( .D( eim_dout_pipe2[8] ),
+// .C( bclk_o ),
+// .Q( eim_dout[8] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eim9( .D( eim_dout_pipe2[9] ),
+// .C( bclk_o ),
+// .Q( eim_dout[9] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eimA( .D( eim_dout_pipe2[10] ),
+// .C( bclk_o ),
+// .Q( eim_dout[10] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eimB( .D( eim_dout_pipe2[11] ),
+// .C( bclk_o ),
+// .Q( eim_dout[11] ),
+// .CE( 1'b1 ), .S(1'b0) );
+//
+// FDSE oddr2_eimC( .D( eim_dout_pipe2[12] ),
+// .C( bclk_o ),
+// .Q( eim_dout[12] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eimD( .D( eim_dout_pipe2[13] ),
+// .C( bclk_o ),
+// .Q( eim_dout[13] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eimE( .D( eim_dout_pipe2[14] ),
+// .C( bclk_o ),
+// .Q( eim_dout[14] ),
+// .CE( 1'b1 ), .S(1'b0) );
+// FDSE oddr2_eimF( .D( eim_dout_pipe2[15] ),
+// .C( bclk_o ),
+// .Q( eim_dout[15] ),
+// .CE( 1'b1 ), .S(1'b0) );
endmodule
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