[Cryptech-Commits] [test/novena_base] 01/01: Merge branch 'coretest_hashes' of git.cryptech.is:test/novena_base into master
git at cryptech.is
git at cryptech.is
Thu Feb 12 23:55:06 UTC 2015
This is an automated email from the git hooks/post-receive script.
paul at psgd.org pushed a commit to branch master
in repository test/novena_base.
commit 8f0faf9fa1ece195eaf102191c571a32d7c1a232
Merge: a758f34 f135907
Author: Paul Selkirk <paul at psgd.org>
Date: Thu Feb 12 18:53:42 2015 -0500
Merge branch 'coretest_hashes' of git.cryptech.is:test/novena_base into master
doc/EIM_Memory_Map.doc | Bin 0 -> 86016 bytes
rtl/build/Makefile | 28 +-
rtl/iseconfig/novena_baseline.xise | 108 +++-
rtl/iseconfig/novena_baseline_top_guide.ncd | 2 +-
rtl/src/ipcore/clkmgr_dcm.gise | 23 +-
rtl/src/ipcore/clkmgr_dcm.ncf | 120 ++--
rtl/src/ipcore/clkmgr_dcm.xise | 339 +----------
rtl/src/testbench/tb_demo_adder.v | 22 +-
rtl/src/ucf/novena_baseline.ucf | 29 +-
rtl/src/verilog/cdc_bus_pulse.v | 199 +++----
rtl/src/verilog/cipher_selector.v | 117 ++++
rtl/src/verilog/core_selector.v | 375 +++++++-----
rtl/src/verilog/demo_adder.v | 108 ----
rtl/src/verilog/eim_arbiter.v | 503 ++++++++--------
rtl/src/verilog/eim_arbiter_cdc.v | 200 ++++---
rtl/src/verilog/eim_da_phy.v | 74 +--
rtl/src/verilog/eim_indicator.v | 49 +-
rtl/src/verilog/eim_memory.v | 182 ++++++
rtl/src/verilog/novena_baseline_top.v | 276 ++++-----
rtl/src/verilog/novena_clkmgr.v | 142 ++---
rtl/src/verilog/novena_regs.v | 126 ++++
rtl/src/verilog/rng_selector.v | 112 ++++
rtl/src/verilog/sha1.v | 204 +++++++
rtl/src/verilog/sha256.v | 204 +++++++
rtl/src/verilog/sha512.v | 241 ++++++++
sw/Makefile | 14 +
sw/hash_tester.c | 876 ++++++++++++++++++++++++++++
sw/novena-eim.c | 708 ++++++++++++++++++++++
sw/novena-eim.h | 52 ++
sw/test-adder/Makefile | 11 -
sw/test-adder/novena-eim.c | 456 ---------------
sw/test-adder/novena-eim.h | 321 ----------
sw/test-adder/test-adder.c | 245 --------
toolruns/ise/novena/novena_baseline_top.bit | Bin 0 -> 1484509 bytes
34 files changed, 4007 insertions(+), 2459 deletions(-)
diff --cc rtl/iseconfig/novena_baseline_top_guide.ncd
index b33fbac,d1b9b4b..dae42ff
--- a/rtl/iseconfig/novena_baseline_top_guide.ncd
+++ b/rtl/iseconfig/novena_baseline_top_guide.ncd
@@@ -1,3 -1,3 +1,3 @@@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
- ###5508:XlxV32DM 3ffb 156ceNqdW9lu28jSfhXhYC7HMnvhFg4MiIscItqGlDMyBoMGtdjRGdvyL8mTBP88/Knmou4S2YntC4n11fJV9d6Uk18Km/8/sYJfss0/28N29/ShR/q89wsNLtgyuLh/2C2LB7F7PvrBxfbpeDh+f9jceUrubQ+b3sVz79vKOTx84/bF6nDPKL9gvYuvvYuH3f12JaN7u7u73sXuofdle/+ld3Hskd7Ft2PP6l3sN/fbw3GzF+uX54ftqjhCDZX3vsd7WgGV8vHYo72L9eZYbB96F9t9pX2unw+rGu++bmrVrve0+2fzVIhlcdg8bJ824rh7Fo/Fc/9pte6y9Z/uu/XPq7seg5bv4ethVQSqdaB4lF+7ByeocgN43hM76Gwe9O3RWQWyg3A3nvoHWsnfXvfKXPc6uAxvhtfjm4VY0FuKIdtokN0SdlfidEqHoVhYt8RZN4oK+sFlHI2 [...]
-###3792:XlxV32DM 3ff4 eb8eNqV2k1vI8cVheG/woW3stW36taHtYrtODAQI0ECA+ZqIGs0YwGyJMwotoP8+ZAzlM2n4CyyGfKQ3XXfqj6n2Zpbn9z01/Gf7fLqk3/c/nz3/u7x4fPd9mndfRJXF+WHq4u3948/XN+/enx6nlcXdw/P75//fX/7Zvz+fnf3/nZ38bT79aa9v/+15sXN+7cl6kXZXfyyu7h/fHt3czx79/jmze7i8X73493bH3cXz7ttd/Hr8+5yd/Hu9u3d++fbd69e/+vp/u7m+vnA8PHod7u6OwP4+OFPz7vYXby+fb6+u99d3L37+OnT6fX+5qQff7k9ffS4e3j8+fbh+tUP1+9v7+8ebl89Pz69+un66dOHm9d/9N2nD2//+POnmze7cpj5u8M/9zfXV7/P7vDBT8d/Hu/b1cfaB/H0bsurP5zeYW2f283VcYFcxt/W5zDL+v9z3/xv7td [...]
++###3792:XlxV32DM 3ff4 eb8eNqV2k1vI8cVheG/woW3stW36taHtYrtODAQI0ECA+ZqIGs0YwGyJMwotoP8+ZAzlM2n4CyyGfKQ3XXfqj6n2Zpbn9z01/Gf7fLqk3/c/nz3/u7x4fPd9mndfRJXF+WHq4u3948/XN+/enx6nlcXdw/P75//fX/7Zvz+fnf3/nZ38bT79aa9v/+15sXN+7cl6kXZXfyyu7h/fHt3czx79/jmze7i8X73493bH3cXz7ttd/Hr8+5yd/Hu9u3d++fbd69e/+vp/u7m+vnA8PHod7u6OwP4+OFPz7vYXby+fb6+u99d3L37+OnT6fX+5qQff7k9ffS4e3j8+fbh+tUP1+9v7+8ebl89Pz69+un66dOHm9d/9N2nD2//+POnmze7cpj5u8M/9zfXV7/P7vDBT8d/Hu/b1cfaB/H0bsurP5zeYW2f283VcYFcxt/W5zDL+v9z3/xv7td [...]
diff --cc rtl/src/ipcore/clkmgr_dcm.gise
index ed6d0f7,4cfaf34..9b267dc
--- a/rtl/src/ipcore/clkmgr_dcm.gise
+++ b/rtl/src/ipcore/clkmgr_dcm.gise
@@@ -26,6 -26,27 +26,27 @@@
<file xil_pn:fileType="FILE_VEO" xil_pn:name="clkmgr_dcm.veo" xil_pn:origination="imported"/>
</files>
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
- <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2136445705273696504" xil_pn:start_ts="1423590634">
++ <transform xil_pn:end_ts="1423783273" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2136445705273696504" xil_pn:start_ts="1423783273">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
- <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5299826667237415001" xil_pn:start_ts="1423590634">
++ <transform xil_pn:end_ts="1423783273" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5299826667237415001" xil_pn:start_ts="1423783273">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
- <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1423590634">
++ <transform xil_pn:end_ts="1423783273" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1423783273">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
- <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2601148782814295670" xil_pn:start_ts="1423590634">
++ <transform xil_pn:end_ts="1423783273" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2601148782814295670" xil_pn:start_ts="1423783273">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ </transforms>
</generated_project>
diff --cc rtl/src/ucf/novena_baseline.ucf
index 6f2d772,cc937f8..c5f4c2c
--- a/rtl/src/ucf/novena_baseline.ucf
+++ b/rtl/src/ucf/novena_baseline.ucf
@@@ -59,59 -59,52 +59,56 @@@ TIMESPEC TS_bclk = PERIOD TNM_bclk 30
#-------------------------------------------------------------------------------
# FPGA Pinout
#-------------------------------------------------------------------------------
-NET "led_pin" LOC = "A16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12 ;
-NET "apoptosis_pin" LOC = "K1" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12 ;
-NET "reset_mcu_b_pin" LOC = "F1" | IOSTANDARD = "LVCMOS33" | PULLUP ;
-
-NET "gclk_p_pin" LOC = "H2" | IOSTANDARD = "LVDS_33" | DIFF_TERM = "TRUE" ;
-NET "gclk_n_pin" LOC = "H1" | IOSTANDARD = "LVDS_33" | DIFF_TERM = "TRUE" ;
-
-NET "eim_bclk" LOC = "C9" | IOSTANDARD = "LVCMOS33" ;
-NET "eim_cs0_n" LOC = "B11" | IOSTANDARD = "LVCMOS33" ;
-
-NET "eim_da<0>" LOC = "G9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<1>" LOC = "A10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<2>" LOC = "F9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<3>" LOC = "B9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<4>" LOC = "E13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<5>" LOC = "F13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<6>" LOC = "A9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<7>" LOC = "A8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<8>" LOC = "B8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<9>" LOC = "D8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<10>" LOC = "D11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<11>" LOC = "C8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<12>" LOC = "C7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<13>" LOC = "C11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<14>" LOC = "C4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET "eim_da<15>" LOC = "B6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-
-NET "eim_a<16>" LOC = "A11" | IOSTANDARD = "LVCMOS33" ;
-NET "eim_a<17>" LOC = "B12" | IOSTANDARD = "LVCMOS33" ;
-NET "eim_a<18>" LOC = "D14" | IOSTANDARD = "LVCMOS33" ;
-
-NET "eim_lba_n" LOC = "B14" | IOSTANDARD = "LVCMOS33" ;
-NET "eim_wr_n" LOC = "C14" | IOSTANDARD = "LVCMOS33" ;
-NET "eim_oe_n" LOC = "C10" | IOSTANDARD = "LVCMOS33" ;
-NET "eim_wait_n" LOC = "A7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-
-NET "ct_led<0>" LOC = K6 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
-NET "ct_led<1>" LOC = H4 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
-NET "ct_led<2>" LOC = H3 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
-NET "ct_led<3>" LOC = M1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
-NET "ct_led<4>" LOC = L7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
-NET "ct_led<5>" LOC = G1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
-NET "ct_led<6>" LOC = T2 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
-NET "ct_led<7>" LOC = H7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
-
-NET "ct_noise" LOC = L4 | IOSTANDARD = LVCMOS33 ;
+NET "led_pin" LOC = "A16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12;
+NET "apoptosis_pin" LOC = "K1" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12;
+NET "reset_mcu_b_pin" LOC = "F1" | IOSTANDARD = "LVCMOS33" | PULLUP;
+
+NET "gclk_p_pin" LOC = "H2" | IOSTANDARD = "LVDS_33" | DIFF_TERM = "TRUE";
+NET "gclk_n_pin" LOC = "H1" | IOSTANDARD = "LVDS_33" | DIFF_TERM = "TRUE";
+
+NET "eim_bclk" LOC = "C9" | IOSTANDARD = "LVCMOS33";
+NET "eim_cs0_n" LOC = "B11" | IOSTANDARD = "LVCMOS33";
+
+NET "eim_da<0>" LOC = "G9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<1>" LOC = "A10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<2>" LOC = "F9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<3>" LOC = "B9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<4>" LOC = "E13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<5>" LOC = "F13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<6>" LOC = "A9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<7>" LOC = "A8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<8>" LOC = "B8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<9>" LOC = "D8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<10>" LOC = "D11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<11>" LOC = "C8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<12>" LOC = "C7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<13>" LOC = "C11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<14>" LOC = "C4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+NET "eim_da<15>" LOC = "B6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+
++NET "eim_a<16>" LOC = "A11" | IOSTANDARD = "LVCMOS33";
++NET "eim_a<17>" LOC = "B12" | IOSTANDARD = "LVCMOS33";
++NET "eim_a<18>" LOC = "D14" | IOSTANDARD = "LVCMOS33";
++
+NET "eim_lba_n" LOC = "B14" | IOSTANDARD = "LVCMOS33";
+NET "eim_wr_n" LOC = "C14" | IOSTANDARD = "LVCMOS33";
+NET "eim_oe_n" LOC = "C10" | IOSTANDARD = "LVCMOS33";
+NET "eim_wait_n" LOC = "A7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12;
+
-
+# Pins to the header where the LEDs on the Cryptech
+# Avalanche Noise Board are connected.
- NET "ct_led[0]" LOC = K6 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
- NET "ct_led[1]" LOC = H4 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
- NET "ct_led[2]" LOC = H3 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
- NET "ct_led[3]" LOC = M1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
- NET "ct_led[4]" LOC = L7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
- NET "ct_led[5]" LOC = G1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
- NET "ct_led[6]" LOC = T2 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
- NET "ct_led[7]" LOC = H7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
++NET "ct_led<0>" LOC = K6 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
++NET "ct_led<1>" LOC = H4 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
++NET "ct_led<2>" LOC = H3 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
++NET "ct_led<3>" LOC = M1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
++NET "ct_led<4>" LOC = L7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
++NET "ct_led<5>" LOC = G1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
++NET "ct_led<6>" LOC = T2 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
++NET "ct_led<7>" LOC = H7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
+
+# Pins to the header where the noise sources on the
+# Cryptech Avalanche Noise Board are connected.
- # Rev 02 schmitt-triggered source.
- NET "ct_noise" | LOC = L4 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
-
- # Rev 02 non schmitt-triggered source. Not used right now.
- # Left here as documentation.
- #NET "ct_noise_F_DX15" | LOC = M5 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
-
++NET "ct_noise" LOC = L4 | IOSTANDARD = LVCMOS33;
#-------------------------------------------------------------------------------
# EIM Input Timing
diff --cc rtl/src/verilog/core_selector.v
index 092a704,eef0a75..093830a
--- a/rtl/src/verilog/core_selector.v
+++ b/rtl/src/verilog/core_selector.v
@@@ -40,145 -40,221 +40,222 @@@
//======================================================================
module core_selector
- (
- input wire sys_clk,
- input wire sys_rst,
-
- input wire ct_noise,
- output wire [07 : 0] ct_led,
-
- input wire [13: 0] sys_eim_addr,
- input wire sys_eim_wr,
- input wire sys_eim_rd,
-
- output wire [31 : 0] read_data,
- input wire [31 : 0] write_data
- );
-
- //
- // Internal Registers
- //
- reg [31: 0] reg_x = {32{1'b0}};
- reg [31: 0] reg_y = {32{1'b0}};
- reg [15: 0] reg_ctl = {16{1'b0}};
- reg [31: 0] read_data_reg = {32{1'b0}};
-
-
- //
- // Parameters
- //
- localparam ADDER_BASE_ADDR = 12'h321; // upper 12 bits of address
- localparam ADDER_OFFSET_REG_X = 2'd0; // X
- localparam ADDER_OFFSET_REG_Y = 2'd1; // Y
- localparam ADDER_OFFSET_REG_Z = 2'd2; // Z
- localparam ADDER_OFFSET_REG_SC = 2'd3; // {STATUS, CONTROL}
-
-
- /* This flag detects whether adder core is being addressed. */
- wire eim_access_adder = (sys_eim_addr[13:2] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0;
-
- /* These flags detect whether write or read access is requested. */
- wire eim_access_write = sys_eim_wr & eim_access_adder;
- wire eim_access_read = sys_eim_rd & eim_access_adder;
-
-
- //
- // Write Request Handler
- //
- always @(posedge sys_clk)
- //
- if (sys_rst) begin
- reg_x <= {32{1'b0}};
- reg_y <= {32{1'b0}};
- reg_ctl <= {16{1'b0}};
- end else if (eim_access_write) begin
- //
- case (sys_eim_addr[1:0])
- ADDER_OFFSET_REG_X: reg_x <= write_data;
- ADDER_OFFSET_REG_Y: reg_y <= write_data;
- ADDER_OFFSET_REG_SC: reg_ctl <= write_data[15 : 0];
- endcase
- //
- end
-
-
- //
- // Read Request Handler
- //
- wire [31: 0] reg_z;
- wire [15: 0] reg_sts;
-
- always @(posedge sys_clk)
- //
- if (sys_rst) read_data_reg <= {32{1'b0}};
- //
- else if (eim_access_read) begin
- //
- case (sys_eim_addr[1:0])
- ADDER_OFFSET_REG_X: read_data_reg <= reg_x;
- ADDER_OFFSET_REG_Y: read_data_reg <= reg_y;
- ADDER_OFFSET_REG_Z: read_data_reg <= reg_z;
- ADDER_OFFSET_REG_SC: read_data_reg <= {reg_sts, reg_ctl};
- endcase
- //
- end
-
- assign read_data = read_data_reg;
-
-
- //
- // Demo Adder Core
- //
- demo_adder adder_core
- (
- .clk (sys_clk),
- .rst (sys_rst),
-
- .x (reg_x),
- .y (reg_y),
- .z (reg_z),
-
- .ctl (reg_ctl),
- .sts (reg_sts)
- );
-
-
- //----------------------------------------------------------------
- // Cryptech Logic
- //
- // Logic specific to the Cryptech use of the Novena.
- // Currently we just sample the noise and drive the LEDs
- // with this signal.
- //----------------------------------------------------------------
- reg ct_noise_sample0_reg;
- reg ct_noise_sample1_reg;
- reg [7 : 0] ct_led_reg;
-
- always @ (posedge sys_clk)
- begin
- if (sys_rst)
- begin
- ct_led_reg <= 8'h00;
- ct_noise_sample0_reg <= 1'b0;
- ct_noise_sample1_reg <= 1'b0;
- end
- else
- begin
- ct_noise_sample0_reg <= ct_noise;
- ct_noise_sample1_reg <= ct_noise_sample0_reg;
- ct_led_reg[0] <= ct_noise_sample1_reg;
- ct_led_reg[1] <= ct_noise_sample1_reg;
- ct_led_reg[2] <= ct_noise_sample1_reg;
- ct_led_reg[3] <= ct_noise_sample1_reg;
- ct_led_reg[4] <= ct_noise_sample1_reg;
- ct_led_reg[5] <= ct_noise_sample1_reg;
- ct_led_reg[6] <= ct_noise_sample1_reg;
- ct_led_reg[7] <= ct_noise_sample1_reg;
- end
- end
-
- assign ct_led = ct_led_reg;
+ (
+ input wire sys_clk,
+ input wire sys_rst,
+ input wire sys_ena,
+
+ input wire [13 : 0] sys_eim_addr,
+ input wire sys_eim_wr,
+ input wire sys_eim_rd,
+ output wire [31 : 0] sys_read_data,
+ input wire [31 : 0] sys_write_data
+ );
+
+
+ /* In this memory segment (HASHES) we have 14 address bits. Every core has
+ * 8-bit internal address space, so we can have up to 2^(14-8) = 64 cores here.
+ *
+ * Core #0 is not an actual HASH core, but a set of board-level (global)
+ * registers, that can be used to get information about hardware (board
+ * type, bitstream version and so on).
+ *
+ * So far we have three cores: SHA-1, SHA-256 and SHA-512.
+ */
+
+ /*********************************************************
+ * To add new HASH core named XXX follow the steps below *
+ *********************************************************
+ *
+ * 1. Add corresponding `define under "List of Available Cores", this will
+ * allow users to exclude your core from implementation to save some
+ * slices in case they don't need it.
+ *
+ * `define USE_CORE_XXX
+ *
+ *
+ * 2. Choose address of your new core and add corresponding line under
+ * "Core Address Table". Core addresses can be in the range from 1 to 63
+ * inclusively. Core address 0 is reserved for a page of global
+ * registers and must not be used.
+ *
+ * localparam CORE_ADDR_XXX = 6'dN;
+ *
+ *
+ * 3. Add instantiation of your new core after all existing cores
+ * surrounded by conditional synthesis directives.
+ * You also need a 32-bit output (read data) bus for your core and an
+ * enable flag. Note that sys_rst in an active-high sync reset signal.
+ *
+ * `ifdef USE_CORE_XXX
+ * wire [31: 0] read_data_xxx;
+ * wire enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX);
+ * xxx xxx_inst
+ * (
+ * .clk(sys_clk),
+ * .reset_n(~sys_rst),
+ * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)),
+ * .we(sys_eim_wr),
+ * .address(addr_core_reg),
+ * .write_data(sys_write_data),
+ * .read_data(read_data_xxx),
+ * .error()
+ * );
+ * `endif
+ *
+ *
+ * 4. Add previously created data bus to "Output (Read Data) Multiplexor"
+ * in the end of this file.
+ *
+ * `ifdef USE_CORE_XXX
+ * CORE_ADDR_XXX:
+ * sys_read_data_mux = read_data_xxx;
+ * `endif
+ *
+ */
+
+
+ //----------------------------------------------------------------
+ // Address Decoder
+ //----------------------------------------------------------------
+ wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed
+ wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core
+
+
+ /* We can comment following lines to exclude cores from implementation
+ * in case we run out of slices.
+ */
+
+ //----------------------------------------------------------------
+ // List of Available Cores
+ //----------------------------------------------------------------
+ `define USE_CORE_SHA1
+ `define USE_CORE_SHA256
+ `define USE_CORE_SHA512
+
+
+ //----------------------------------------------------------------
+ // Core Address Table
+ //----------------------------------------------------------------
+ localparam CORE_ADDR_GLOBAL_REGS = 6'd0;
+ localparam CORE_ADDR_SHA1 = 6'd1;
+ localparam CORE_ADDR_SHA256 = 6'd2;
+ localparam CORE_ADDR_SHA512 = 6'd3;
+
+
+ //----------------------------------------------------------------
+ // Global Registers
+ //----------------------------------------------------------------
+ wire [31: 0] read_data_global;
+ wire enable_global = sys_ena && (addr_core_num == CORE_ADDR_GLOBAL_REGS);
+ novena_regs novena_regs_inst
+ (
+ .clk(sys_clk),
+ .rst(sys_rst),
+
+ .cs(enable_global & (sys_eim_rd | sys_eim_wr)),
+ .we(sys_eim_wr),
+
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
+ .read_data(read_data_global)
+ );
+
+
+ //----------------------------------------------------------------
+ // SHA-1
+ //----------------------------------------------------------------
+ `ifdef USE_CORE_SHA1
+ wire [31: 0] read_data_sha1;
+ wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1);
+ sha1 sha1_inst
+ (
+ .clk(sys_clk),
+ .reset_n(~sys_rst),
+
+ .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)),
+ .we(sys_eim_wr),
+
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
+ .read_data(read_data_sha1)
+ );
+ `endif
+
+
+ //----------------------------------------------------------------
+ // SHA-256
+ //----------------------------------------------------------------
+ `ifdef USE_CORE_SHA256
+ wire [31: 0] read_data_sha256;
+ wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256);
+ sha256 sha256_inst
+ (
+ .clk(sys_clk),
+ .reset_n(~sys_rst),
+
+ .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)),
+ .we(sys_eim_wr),
+
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
+ .read_data(read_data_sha256)
+ );
+ `endif
+
+
+ //----------------------------------------------------------------
+ // SHA-512
+ //----------------------------------------------------------------
+ `ifdef USE_CORE_SHA512
+ wire [31: 0] read_data_sha512;
+ wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512);
+ sha512 sha512_inst
+ (
+ .clk(sys_clk),
+ .reset_n(~sys_rst),
+
+ .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)),
+ .we(sys_eim_wr),
+
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
+ .read_data(read_data_sha512)
+ );
+ `endif
+
+
+ //----------------------------------------------------------------
+ // Output (Read Data) Multiplexor
+ //----------------------------------------------------------------
+ reg [31: 0] sys_read_data_mux;
+ assign sys_read_data = sys_read_data_mux;
+
+ always @*
+ //
+ case (addr_core_num)
+ //
+ CORE_ADDR_GLOBAL_REGS:
+ sys_read_data_mux = read_data_global;
+ `ifdef USE_CORE_SHA1
+ CORE_ADDR_SHA1:
+ sys_read_data_mux = read_data_sha1;
+ `endif
+ `ifdef USE_CORE_SHA256
+ CORE_ADDR_SHA256:
+ sys_read_data_mux = read_data_sha256;
+ `endif
+ `ifdef USE_CORE_SHA512
+ CORE_ADDR_SHA512:
+ sys_read_data_mux = read_data_sha512;
+ `endif
+ //
+ default:
+ sys_read_data_mux = {32{1'b0}};
+ //
+ endcase
+
+
endmodule
//======================================================================
diff --cc toolruns/ise/novena/novena_baseline_top.bit
index 0000000,eb0b362..7b5dabb
mode 000000,100644..100644
Binary files differ
More information about the Commits
mailing list