[Open Crypto Project] #6: verilator warnings for novena builds

[Open Crypto Project]

#6: verilator warnings for novena builds
--------------------+----------------------
 Reporter:  sra     |      Owner:  pselkirk
     Type:  defect  |     Status:  new
 Priority:  minor   |  Milestone:
Component:  rtl     |    Version:
 Keywords:          |
--------------------+----------------------
 `verilator --lint` reported the following warnings, passing them along in
 case they're relevant.

 `core/novena` build:
 {{{
 %Warning-WIDTH: ../../sha512/src/rtl/sha512_w_mem.v:333: Operator EQ
 expects 7 bits on the RHS, but RHS's CONST '6'h3f' generates 6 bits.
 %Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around
 source to disable this message.
 %Warning-WIDTH: ../../sha1/src/rtl/sha1_w_mem.v:290: Operator ASSIGN
 expects 7 bits on the Assign RHS, but Assign RHS's CONST '6'h0' generates
 6 bits.
 %Warning-WIDTH: ../../coretest/src/rtl/coretest.v:366: Logical Operator IF
 expects 1 bit on the If, but If's VARREF 'cmd_we' generates 8 bits.
 }}}

 `core/novena_i2c_simple` build:
 {{{
 %Warning-WIDTH: ../../sha512/src/rtl/sha512_w_mem.v:333: Operator EQ
 expects 7 bits on the RHS, but RHS's CONST '6'h3f' generates 6 bits.
 %Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around
 source to disable this message.
 %Warning-WIDTH: ../../sha1/src/rtl/sha1_w_mem.v:290: Operator ASSIGN
 expects 7 bits on the Assign RHS, but Assign RHS's CONST '6'h0' generates
 6 bits.
 %Warning-WIDTH: ../src/rtl/sha512.v:183: Bit extraction of array[63:0]
 requires 6 bit index, not 7 bits.
 %Warning-WIDTH: ../src/rtl/sha512.v:281: Operator LT expects 32 or 11 bits
 on the LHS, but LHS's VARREF 'i' generates 8 bits.
 %Warning-WIDTH: ../src/rtl/sha512.v:282: Bit extraction of array[127:0]
 requires 7 bit index, not 8 bits.
 %Warning-WIDTH: ../src/rtl/sha512.v:401: Operator EQ expects 32 or 11 bits
 on the LHS, but LHS's VARREF 'rx_ptr_new' generates 8 bits.
 %Warning-WIDTH: ../src/rtl/sha512.v:481: Operator EQ expects 32 or 9 bits
 on the LHS, but LHS's VARREF 'tx_ptr_new' generates 8 bits.
 %Warning-WIDTH: ../src/rtl/sha512.v:482: Operator EQ expects 32 or 9 bits
 on the LHS, but LHS's VARREF 'tx_ptr_new' generates 8 bits.
 %Warning-WIDTH: ../src/rtl/sha512.v:483: Operator EQ expects 32 or 10 bits
 on the LHS, but LHS's VARREF 'tx_ptr_new' generates 8 bits.
 %Warning-WIDTH: ../src/rtl/sha256.v:155: Bit extraction of array[31:0]
 requires 5 bit index, not 7 bits.
 %Warning-WIDTH: ../src/rtl/sha256.v:220: Operator LT expects 32 or 10 bits
 on the LHS, but LHS's VARREF 'i' generates 8 bits.
 %Warning-WIDTH: ../src/rtl/sha256.v:221: Bit extraction of array[63:0]
 requires 6 bit index, not 8 bits.
 %Warning-WIDTH: ../src/rtl/sha256.v:249: Bit extraction of array[63:0]
 requires 6 bit index, not 7 bits.
 %Warning-WIDTH: ../src/rtl/sha256.v:340: Operator EQ expects 32 or 10 bits
 on the LHS, but LHS's VARREF 'rx_ptr_new' generates 8 bits.
 %Warning-WIDTH: ../src/rtl/sha256.v:419: Operator EQ expects 32 or 9 bits
 on the LHS, but LHS's VARREF 'tx_ptr_new' generates 8 bits.
 %Warning-WIDTH: ../src/rtl/sha1.v:155: Bit extraction of array[19:0]
 requires 5 bit index, not 7 bits.
 %Warning-WIDTH: ../src/rtl/sha1.v:208: Operator LT expects 32 or 10 bits
 on the LHS, but LHS's VARREF 'i' generates 8 bits.
 %Warning-WIDTH: ../src/rtl/sha1.v:209: Bit extraction of array[63:0]
 requires 6 bit index, not 8 bits.
 %Warning-WIDTH: ../src/rtl/sha1.v:237: Bit extraction of array[63:0]
 requires 6 bit index, not 7 bits.
 %Warning-WIDTH: ../src/rtl/sha1.v:328: Operator EQ expects 32 or 10 bits
 on the LHS, but LHS's VARREF 'rx_ptr_new' generates 8 bits.
 }}}

 `core/novena_eim` build:
 {{{
 %Warning-IMPLICIT: ../src/rtl/ip/dcm_delay/dcm_delay.v:88: Signal
 definition not found, creating implicitly: clkin1
 %Warning-IMPLICIT: Use "/* verilator lint_off IMPLICIT */" and lint_on
 around source to disable this message.
 %Warning-IMPLICIT: ../src/rtl/ip/bclk_dll/bclk_dll.v:80: Signal definition
 not found, creating implicitly: clkin1
 %Warning-IMPLICIT: ../src/rtl/novena_fpga.v:413: Signal definition not
 found, creating implicitly: slowclk
 %Warning-IMPLICIT: ../src/rtl/novena_fpga.v:432: Signal definition not
 found, creating implicitly: i_locked
 %Warning-WIDTH: ../../sha1/src/rtl/sha1_w_mem.v:290: Operator ASSIGN
 expects 7 bits on the Assign RHS, but Assign RHS's CONST '6'h0' generates
 6 bits.
 %Warning-WIDTH: ../../sha512/src/rtl/sha512_w_mem.v:333: Operator EQ
 expects 7 bits on the RHS, but RHS's CONST '6'h3f' generates 6 bits.
 }}}

 There's also quite a bit of whining about modules verilator can't find,
 but I think that's just because it doesn't know about the !XiLinx library.
 There's probably some way to tell it about the library, I just don't (yet)
 know what it is.

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Ticket URL: <https://trac.cryptech.is/ticket/6>
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