<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto"><div>There is no need in delayering chip, because the design _is_ open<br><br>dol@ с iPad</div><div><br>12 янв. 2015 г., в 1:23, Шатов Павел <<a href="mailto:meisterpaul1@yandex.ru">meisterpaul1@yandex.ru</a>> написал(а):<br><br></div><blockquote type="cite"><div><div>Yes, that is exactly what I was talking about. Delayering a chip is much harder than simply piercing soldermask with a sharp digital analyzer probe. If you are going to have C-4 onboard, this factor is not that important of course :)</div><div> </div><div><div>-- <br>With best regards,</div><div>Paul Shatov</div><div> </div></div><div>11.01.2015, 23:53, "Joachim Strömbergson" <<a href="mailto:joachim@secworks.se">joachim@secworks.se</a>>:</div><blockquote type="cite"><p><br><br>Aloha!<br><br>Yes, adding a soft core is one option we have for the future. Using a<br>hard core such as Xilinx Zync or Altera SoCs adds a lot of performance,<br>but it reduces the ability to actually test and know as well as limit<br>what is actually accessible from where.<br><br>In terms of side channel leakage, having an internal interface on chip<br>is better than having an interface over the PCB. But this interface will<br>be inside the tamper boundary.<br><br>For the next, next generation board (or later revisions of this one) we<br>may move to an integrated solution. But for the platform after Novena I<br>think our assumption right now is that we really want to have separate<br>physical devices. This is because it allows us to decompose the system<br>into separate partitions that can more easily be controlled and audited.<br><br>Cheers<br>JoachimS<br><br>Шатов Павел wrote:</p><blockquote> Hello everyone. I haven't attended your meeting, so I don't know all<br> the underlying details of your discussion. Do you intentionally want<br> your board to include CPU and FPGA as two separate chips? As far as I<br> know in terms of hardware security having one single integrated<br> circuit is better. Two options are possible to combine both CPU and<br> FPGA in one physical IC. The first option is to select larger FPGA<br> and add some processor IP core to it. Both Altera and Xilinx provide<br> soft processors, but they are not opensource. I believe there might<br> be suitable soft processors available at <br> <a href="http://opencores.org/projects">http://opencores.org/projects</a>. The drawback of this approach is that<br> such soft processors will not run very fast. I've mostly worked with<br> Spartan-6, from my experience it is difficult to push MicroBlaze from<br> Xilinx beyond 125-133 MHz. Other processors should be about the same.<br> On the other hand you can configure soft processor to only include<br> modules that you actually need. The second option is to use some PSoC<br> chip. I can suggest having a look at Zynq from Xilinx: <br> <a href="http://www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-table.pdf">http://www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-table.pdf</a>.<br> It has dual-core ARM Coretex-A9 CPU and Artix/Kintex FPGA in one<br> package. There are several other PSoC vendors too, Zynq is just an<br> example. From my experience programmable system-on-chip projects<br> require much initial effort, but as the project matures it becomes<br> easier to develop <br> it.<<a href="http://www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-table.pdf">http://www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-table.pdf</a>></blockquote><p>11.01.2015, 12:18, "Fredrik Thulin" <<a href="mailto:fredrik@thulin.net">fredrik@thulin.net</a></p><blockquote> <mailto:<a href="mailto:fredrik@thulin.net">fredrik@thulin.net</a>>>:<br><blockquote> It seems to me that the interface between the FPGA and ARM will be<br> one of the real selectors for what ARM to use?<br><br> Joachim, can you make a baseline suggestion for what FPGA to use<br> and what interface to use?<br><br> I remember from the meeting last week that we said we are currently<br> using about 70% of the resources in the Novena FPGA and would aim<br> for something 10x (?) bigger for the alpha board, to not be space<br> constrained during development?<br><br> /Fredrik<br><br> _______________________________________________ Tech mailing list <br> <a href="mailto:Tech@cryptech.is">Tech@cryptech.is</a> <mailto:<a href="mailto:Tech@cryptech.is">Tech@cryptech.is</a>> <br> <a href="https://lists.cryptech.is/listinfo/tech">https://lists.cryptech.is/listinfo/tech</a></blockquote> -- With best regards, Paul Shatov<br><br> _______________________________________________ Tech mailing list <br> <a href="mailto:Tech@cryptech.is">Tech@cryptech.is</a> <a href="https://lists.cryptech.is/listinfo/tech">https://lists.cryptech.is/listinfo/tech</a></blockquote><p>- -- <br>Med vänlig hälsning, Yours<br><br>Joachim Strömbergson - Alltid i harmonisk svängning.<br>========================================================================<br> Joachim Strömbergson Secworks AB <a href="mailto:joachim@secworks.se">joachim@secworks.se</a><br>========================================================================</p><blockquote>-----BEGIN PGP SIGNATURE-----<br>Version: GnuPG/MacGPG2 v2<br>Comment: GPGTools - <a href="http://gpgtools.org/">http://gpgtools.org</a><br>Comment: Using GnuPG with Mozilla - <a href="http://enigmail.mozdev.org/">http://enigmail.mozdev.org/</a><br><br>iQIcBAEBCAAGBQJUsuLAAAoJEF3cfFQkIuyNRJMQAL75OY0Ym9gewX6Rge4YFIoM<br>DpMCQEgLJZGQKiGUOxGaJ3EovtI9ThiVa1S+l5HQH+na6y9mwMi0XAZBbc6GP4hb<br>UmDPBUVXPGYsqT5Er6lbc2yBdLsW+cHsjBMWnTQtQFvDi0geTVO3pdSpieljjmTT<br>d3xdI9kUfvjgYzNZ9cwGI85yniaV6EKsagNndY8M9/jrfS3oI4I2qwFcvzsXPUJP<br>w4+QxY+ce6/V6s0ke2lHIpzy0zIziVLRp433/zSQj1f7F2+9JwdwynZCmEqAg375<br>s3NKDL5HHwcMDpEww7uBksgp7h+U5HEC8KMVPYUDw/MqX5WKaOUQikgwqHCkNy7d<br>/Nk4igp4GV0cG8KMyzy21HYAScPCOvx0mM2pWwuIs9qFL66RJYxR5wXeaOn3lWWV<br>aRyWxSITJ/UlCixYOHrJsh6/BzHC/hxT73C392bJyb17nSIq4arK/etJihNgGRf9<br>RMloJRUKaOSHKCuiXiZXk4a3aqah7b+b3QMeLL+OWfBYXSWOk3DYL+y2NTSKtOno<br>+yahUqUCJzh+ISWqGltpeo94ckMxllcGgLUTribUqnmhHUD+rVGVhMYjg2kmoFS8<br>vshgg0PKMysPY90oAMs2G40gJS9eKaBrNUYFoXLcJz/ALFbfoA+sb9wO/M+75OaV<br>EEMMI8YzhNQldYmVnqEi<br>=Une+<br>-----END PGP SIGNATURE-----</blockquote></blockquote><div> </div><div> </div></div></blockquote><blockquote type="cite"><div><span>_______________________________________________</span><br><span>Tech mailing list</span><br><span><a href="mailto:Tech@cryptech.is">Tech@cryptech.is</a></span><br><span><a href="https://lists.cryptech.is/listinfo/tech">https://lists.cryptech.is/listinfo/tech</a></span><br></div></blockquote></body></html>