<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Dear Joachim,<div><br></div><div>I am not building a new CPU from scratch, it is useless, I am using OpenRISC as a base code, and customizing it.</div><div>I would to come closer from Forth (And also Bernd) as long as we are working on very similar things.</div><div><br></div><div>Building a TOR processor, a non-micro-coded processor, a pure hard coded logic controller, is from far the best approach to reduce the attack surface to the minimum level.</div><div><br></div><div>This is very encouraging.</div><div><br></div><div><br><div><div>Le 6 août 2014 à 13:52, Joachim Strömbergson <<a href="mailto:joachim@secworks.se">joachim@secworks.se</a>> a écrit :</div><br class="Apple-interchange-newline"><blockquote type="cite"><fieldset style="padding-top:10px; border:0px; border: 3px solid #CCC; padding-left: 20px;"><legend style="font-weight:bold">Signé partie PGP</legend><div style="padding-left:3px;">Aloha!<br><br>★ STMAN ★ wrote:<br>> Thank you very much for your contribution Bernd, I fully agree with<br>> all what you said. C language is a problem, but it is also a<br>> standard. Correcting efficiently C language « weaknesses » like<br>> intensive stack usage cannot be achieved securely through software<br>> technics : StackShield and StackGuard technics have partly failed,<br>> and they don’t block ROP exploitation.<br>><br>> Let’s say that for the first version of the secure processor, the<br>> main goals were to « cancel » by design, from the hardware :<br>><br>> - Stack Overflow security breach. - Buffer Overflow security breach.<br>><span class="Apple-converted-space"> </span> - ROP exploitation technics.<br>><br>> It has been more than one year study to find the tricks to do it<br>> definitly.<br>><br>> The planned next step, in the future, are to block the « Interger<br>> Overflow » familly security breach, and reaching the goals you are<br>> talking about.<br><br>Are you doing this by defining a CPU from scratch with your own ISA, or<br>are you basing the work on an existing core?<br><br>If I were to do this I would select a CPU core that have GCC etc ported<br>to it (OpenRISC, LEON etc) and then implement them one by one, modifying<br>the HW design, adding functionality to the core and updating the SW<br>system one by one. This way you can test and integrate the new<br>functionality in the application SW one by one.<br><br>--<br>Med vänlig hälsning, Yours<br><br>Joachim Strömbergson - Alltid i harmonisk svängning.<br>========================================================================<br> Joachim Strömbergson<span class="Apple-converted-space"> </span> <span class="Apple-converted-space"> </span> <span class="Apple-converted-space"> </span> <span class="Apple-converted-space"> </span> <span class="Apple-converted-space"> </span> Secworks AB<span class="Apple-converted-space"> </span> <span class="Apple-converted-space"> </span> <span class="Apple-converted-space"> </span> <span class="Apple-converted-space"> </span> <span class="Apple-converted-space"> </span> <a href="mailto:joachim@secworks.se">joachim@secworks.se</a><br>========================================================================</div></fieldset><br></blockquote></div><br></div></body></html>