<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Thank for this information.<div> </div><div>I am going to have a look at this board and let you know my understanding of its possibilities.</div><div> <div><div>Le 1 août 2014 à 17:17, Joachim Strömbergson <<a href="mailto:joachim@secworks.se">joachim@secworks.se</a>> a écrit :</div> <blockquote type="cite"><fieldset style="padding-top:10px; border:0px; border: 3px solid #CCC; padding-left: 20px;"><legend style="font-weight:bold">Signé partie PGP</legend><div style="padding-left:3px;">Aloha! Thanks for good comments and thoughts. ★ STMAN ★ wrote: > As you requested me, here are my comments and remarks about a > Roadmap and « What would happen if we wanted to develop a secure TOR > Router on the Novena as is » : > > Indeed there are other facts that you must know about the Novena and > the problems that would rise to build a secure TOR EndPoint (With 1 > dedicated Ethernet port), or a secure TOR router / firewall (With 2 > dedicated Ethernet Ports): > > In order to use it as a prototyping/development platform, I am now > convinced it is not the best choice to have : Do you see it as not useful even for development purpose? We do also develop the Cryptech HW using dedicated FPGA boards like the TerasIC C5G board. For Tor this might be a more suitable solution where we can lock down the FPGA configuration, provide local physical and electrical mechanisms that blocks remote tampetering (and local tamper detect). <a href="http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=830">http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=830</a> The board is not equipped with any Ethernet interfaces, but these can be added using a separate extension board. Either one we design ourselves or using a ready made (if that is ok): http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=71&No=355 For the SW/control part we can either add a separate CPU/MCU or include a CPU core in the FPGA design. -- Med vänlig hälsning, Yours Joachim Strömbergson - Alltid i harmonisk svängning. ======================================================================== Joachim Strömbergson Secworks AB joachim@secworks.se ========================================================================</div></fieldset> </blockquote></div> </div></body></html>