[Cryptech Tech] Selection of Lattice FPGA as key memory for the Alpha board

[Joachim Strömbergson]

Aloha!

Continuing regarding programming. Writing to the NVCM seems to be done
in three ways:

1. Using a Lattice Diamond Programmer attached to the hard SPI interface
in the device. At least some pads or a header on the board would be
required. And getting a Diamong Programmer.

2. From a CPU host. In Alpha board context this would either be an
external host (connected via a header), the STM32, or via the big FPGA.
Unfortunately how this is to be done is not specified. "For more
information contact your local Lattice sales office."

3. Have the chips be programmed by Lattice prior to delivery. This would
probably require a minimum volume greater than what we plan for. More
importantly, I don't see us wanting a third party programming the master
key handling and tamper response functionality for us. That would be yet
a new black box.

So, either 1 or 2. There is also the ability to load the config directly
from an external source (including a host), that is not writing to the
NVCM. This is how the iCESTICK works. At least for testing. An incorrect
write to the NVCM would have quite severe impact.

Regards,
JoachimS

On 2020-03-26 11:19, Joachim Strömbergson wrote:
> Aloha!
> 
> Replying to myself here. Reading up on device programming I found an issue:
> 
> [iCE40 Programming and
> Configuration](http://www.latticesemi.com/view_document?document_id=46502)
> 
> It turns out that the LM versions of iCE40 lacks the in-package
> non-volatile configuration memory (NVCM). We want to have this memory.
> This removes the LM-device below from the list of candidates. The
> LP-versions includes the NVCM.
> 
> Regards,
> JoachimS
> 
> 
> On 2020-03-24 16:34, Joachim Strömbergson wrote:
>> Aloha!
>>
>> (Lets do this on @tech. Hopefully somebody else want to chime in with
>> suggestions and ideas.)
>>
>> Pavel, I’ve looked at possible FPGA devices to be integrated onto the
>> new Cryptech board to be used as FPGA based master key memory
>> (fpga_mkm). Here are my reasoning for the devices I’ve selected.
>>
>> We want to use a device supported by the Project IceStorm toolchain:
>> [Project IceStorm"](http://www.clifford.at/icestorm/). The toolchain
>> supports a number of devices in the iCE40 LP/HX/LM series:
>> https://www.latticesemi.com/Products/FPGAandCPLD/iCE40
>>
>> We are currently using the iCEstick evaluation board for the
>> development. The iCEstick is supported by the toolchain. [iCEstick
>> Evaluation Kit - Lattice
>> Semiconductor](http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCEstick).
>>
>> The dev board sports a iCE40HX1K device. Judging by resource numbers we
>> are currently using 15% of the Programmable Logic Blocks. This means
>> that we could use a smaller device. But the 1K-devices contain an PLL
>> that can be used as clock source (meaning no external clock). I would
>> therefore suggest that we choose one of the 1K-devices.
>>
>> We also need very few I/Os. We currently use nine I/Os, and one is for
>> clock and two are just for debugging (red and green LEDs)
>>
>> Based on this, and looking at availability, I have the following LP1L
>> devices on my list:
>>
>> * [ICE40LP1K-SWG16TR Lattice Semiconductor Corporation | Integrated
>> Circuits (ICs) |
>> DigiKey](https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40LP1K-SWG16TR/ICE40LP1K-SWG16TR-ND/4572398).
>>
>> * [ICE40LP1K-CM36 Lattice Semiconductor Corporation | Integrated
>> Circuits (ICs) |
>> DigiKey](https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40LP1K-CM36/220-1564-ND/3083574)
>>
>> The 16-ball WLCSP has 0.35 mm spacing and the 36-ball ucBGA has 0.40 mm
>> spacing.
>>
>> From LM1K I would suggest:
>> * [ICE40LM1K-SWG25TR Lattice Semiconductor Corporation | Integrated
>> Circuits (ICs) |
>> DigiKey](https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40LM1K-SWG25TR/ICE40LM1K-SWG25TR-ND/4572404)
>>
>> The 25-ball WLCSP has 0.35 mm spacing.
>>
>> All devices seems to be in active production and accessible in single
>> quantities for around 3 USD. Do you think any of these would work?
>> Anyone that you prefer?
>>
>> I haven’t looked at how we are going to program the devices on the
>> board. The devices contain a Flash based config memory that can be
>> programmed and then locked. This is a feature we want to use.
>>
>>
>> _______________________________________________
>> Tech mailing list
>> Tech at cryptech.is
>> https://lists.cryptech.is/listinfo/tech
>>
> 
> 
> 
> _______________________________________________
> Tech mailing list
> Tech at cryptech.is
> https://lists.cryptech.is/listinfo/tech
> 


-- 
Med vänlig hälsning, Yours

Joachim Strömbergson
========================================================================
                               Assured AB
========================================================================

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: OpenPGP digital signature
URL: <https://lists.cryptech.is/archives/tech/attachments/20200326/e4970d50/attachment.sig>