[Cryptech Tech] Happier RSA timing numbers

[Joachim Strömbergson]

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Aloha!

Rob Austein wrote:
> On Wed, 23 May 2018 01:34:28 -0400, Joachim Strömbergson wrote:
>> Since you are running w parallel AES cores that way of improving 
>> things is already used. The next thing should be double sys_clk to
>>  100 MHz. That should drop the wait time.

I think I can shave off one more cycle/ECB operation (whoopie!).

But lets focus on getting 100 MHz to work. Pavel pointed to
alpha_fmc_top.v and two lines to change. Those lines are 78 and 79:

  .CLK_OUT_MUL      (20.0),    // 2..64
  .CLK_OUT_DIV      (20.0)     // 1..128

As I see it, changing either one should be enough, as long as we stay
within the given limits. For example dropping DIV to 10.0. I asked Pavel
several days ago to confirm or correct this. But haven't gotten a response.

Pavel: Would dropping DIV to 10.0 be ok? Or do we need to adjust both,
for example to 32.0 for MUL and 16.0 for DIV?

I can create a branch for this for you Rob to check out and use when we
know.

- -- Med vänlig hälsning, Yours

Joachim Strömbergson - Assured AB
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