[Cryptech Tech] Happier RSA timing numbers

[Joachim Strömbergson]

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Aloha!

Rob Austein wrote:
> On Mon, 21 May 2018 13:14:04 -0400, Joachim Strömbergson wrote:
>> There is now a new AES core in the Cryptech repo: aes_speed.
> 
> Thanks!  Will profile if it gets that far (first attempt to
> synthesis the combined bitstream failed, don't know why yet).

The aes_speed core has now been optimized to take one cycle/round for
encipher and decipher operations. I have implemented it in Xilinx ISE
for Artix7 several times and it looks good.  Do you know what caused the
synthesis failed?

The next two possible things to change to optimize the core are to:

1. Optimize the key expansion. But unless you change keys often, this
will not add very much.

2. Pipelining the core. This will increase throughput, but will (I'm
sure) increase the size. Performance for a given single block will of
course not be better.

Since you seemed to use multiple AES cores that basically provides the
same performance increase as (2).

So, right now I don't see any major additional changes to the aes core
itself. Lets get new profile results and then see what we need to
improve. We still haven't increased the core clock speed to 100 MHz
which should increase performance too.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Assured AB
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