[Cryptech Tech] Happier RSA timing numbers

[Joachim Strömbergson]

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Aloha!

Joachim Strömbergson wrote:
> Aloha!
> 
> Rob Austein wrote:
>> For future reference: a branch of the existing aes repository
>> would have been much simpler to test than a whole new repository.
> 
> I did considered that, but decided that having two separate cores
> with different architectures would be much less confusing.

To clarify: I expected that the aes core optimized for speed would be so
much larger (in terms of resources used) that we would never merge it
into the normal aes core. My experience is that having two quite
different architectures and designs in the same repo in different
branches that never merge will lead to confusion. Normally the one not
being the master will be lost, forgotten, not found etc. Even if you try
to be very explicit in branch naming, documentation etc.


But I have now done some synthesis runs of the aes_speed core and
compared it to the normal aes core. I think that we could consider
replacing the aes core with aes_speed.

Results for Xilinx Artix7-t200.

Old core (aes)
- - 2102 slices
- - 2991 regs
- - 113 MHz (8.79ns)

New core (aes_speed)
- - 2019 slices
- - 2984 regs
- - 131 MHz. (7.58ns)

The better clock speed and a few less registers isn't surprising. A
couple of MUXes to provide S-box sharing within the encipher path and
between encipher and key expansion has been removed.

But the number of slices is a bit surprising. The mapping tool seems to
do a great job mapping the S-boxes. For reference, I've done a similar
modification of the AES core for an ASIC-implementation, and there we
could see an increase in cells as the number of S-boxes increased.


So, we need to test the AES core in the actual FPGA. If it works we
should probably replace the old aes core with the design in aes_speed.


One thing I will do right away is to further optimize performance and do
cycle measurements between aes and aes_speed.

This is fun!
- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Assured AB
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