[Cryptech Tech] Happier RSA timing numbers

Joachim Strömbergson joachim.strombergson at assured.se
Mon May 21 17:14:04 UTC 2018


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Aloha!

Rob Austein wrote:
> On Sat, 19 May 2018 01:38:37 -0400, Joachim Strömbergson wrote: ...
>> I can build a modified version of the AES core with 16 Sboxes.
>> This should cut those 98 seconds to 25 or so. That is fairly easy
>> to do and I can start doing that on Tuesday. Ok?
> 
> Sure.

There is now a new AES core in the Cryptech repo: aes_speed.

https://trac.cryptech.is/browser/core/cipher/aes_speed

This core sports 16 S-boxes each for encipher and decipher. The core
simulates ok. For single block AES-128 the number of cycles is 21
compared to 57 for the regular AES core. That is a performance increase
of 2.1x. For multi block messages the performance increase should be
even better. And this should at least be good enough to test that this
improves the RSA timings.

The actual core module names are the same, so you should be able to use
this core by simply using its files instead of the old one.

I have yet to perform FPGA implementation of the new core, so I don't
yet know how much bigger it is. I will do that tomorrow. By doing that I
will also be able to see what the clock frequency numbers looks like. If
they are as expected I will try to coalesce all round operations into a
single clock cycle. This will double the performance again to reach the
expected 4x.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Assured AB
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