[Cryptech Tech] Seeking comments on a proposal for changes to the Cryptech RNG design.

[Joachim Strömbergson]

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Aloha!

Benny Baumann wrote:
> OT: Has an entropy source like WhirlyGig[1] or some FPGA port of 
> it[2] been considered as an additional entropy source? Having 
> experimented with that code on some Papillio Pro board a while ago I 
> found the general design to provide good results with dieharder when 
> sending samples at 2Mbps. The bit stream could easily be scaled to 
> provide 1Gbps; although I didn't try this due to lack of means to 
> transfer data fast enough (The WhirlyGig core runs easily at 100MHz 
> on the Papillio Pro).

I've looked at Whirlygig. It is basically a number of free running
digital oscillators (inverters) that are sampled. This is how the rosc
entropy source in the Cryptech RNG works. Designed by Bernd Paysan. The
rosc contains 32 separate free running digital oscillators that are
sampled and XOR-combined every 256 cycles.

Note that we second entropy source based on avalanche noise in a PN
junction. Designed by Fredrik Thulin.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Assured AB
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