[Cryptech Tech] Key wrap in HW

[Joachim Strömbergson]

Aloha!

On 18 Jun 2018, at 19:04, Rob Austein wrote:
> /*
>  * Sizes for PKCS #8 encoded private keys.  This may not be exact due
>  * to ASN.1 INTEGER encoding rules, but should be good enough for
>  * buffer sizing.
>  *
>  * 2048-bit RSA:        1219 bytes
>  * 4096-bit RSA:        2373 bytes
>  * 8192-bit RSA:        4679 bytes
…

Almost 5000 bytes for a 8192 bit key. That is 4.5x more data and the key length in bits.
Divided into 64 bit blocks on which the key wrap operates, that is 585 blocks. Each block is transferred 12 times between the MCU and the FPGA (if one counts the cipher text for the block to be the same block). And for each transfer there is a spin-wait for the AES core to signal ready after processing the block. I think there is an opportunity to improve matters here.

Regards,
JoachimS
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