[Cryptech Tech] fpga speed

Joachim Strömbergson joachim.strombergson at assured.se
Thu Jun 14 07:56:50 UTC 2018


On 13 Jun 2018, at 18:55, Michael wrote:
> I posted a couple video clips on Cryptech #hardware so I wont repeat them here. Bottom line is that you can see an increase in the frequency of rdenable | wrenable which is assigned to the LED. However the increase in sigs/sec is marginal +0.2 sigs/sec.
> I also recompile the .bit file with DEFAULT_SCLK_DIV = 8'h0010, with no measurable difference.
> Not sure where to go from here. I will have my frequency counter tomorrow, so if I can get some help on the RTL to assign sclk to a GPIO I can measure the exact frequency. It kind of feels to me like there is a bottleneck somewhere else that is not dependent on sclk.......

I just pushed a new branch of the alpha platform repo called gpio_led_toggle.

In the branch I’ve connected the GPIO banks on the board to the FPGA.

I’ve also added a toggle circuit that should output a divided down version of the sys_clk. This version of sys_clk should be accessible on pin 0 on both banks. If my calculations are correct, the clock frequency should be 500 kHz when running sys_clk at 50 MHz. And 1 MHz if sys_clk is running at 100 MHz.

Please check it out (literally ;-)

(I have simulated the toggle circuit, but not built a complete FPGA.)

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