[Cryptech Tech] fpga speed

Joachim Strömbergson joachim.strombergson at assured.se
Wed Jun 13 17:55:25 UTC 2018


Thanks for the status update. I’ll create a RTL tomorrow.

> On 13 Jun 2018, at 18:55, Michael <dockter at dkey.org> wrote:
> I posted a couple video clips on Cryptech #hardware so I wont repeat them here. Bottom line is that you can see an increase in the frequency of rdenable | wrenable which is assigned to the LED. However the increase in sigs/sec is marginal +0.2 sigs/sec.
> I also recompile the .bit file with DEFAULT_SCLK_DIV = 8'h0010, with no measurable difference.
> Not sure where to go from here. I will have my frequency counter tomorrow, so if I can get some help on the RTL to assign sclk to a GPIO I can measure the exact frequency. It kind of feels to me like there is a bottleneck somewhere else that is not dependent on sclk.......
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