[Cryptech Tech] Cleanup of chacha

Joachim Strömbergson joachim at secworks.se
Tue Jan 3 12:06:43 UTC 2017


Peter Stuge wrote:
> Joachim Strömbergson wrote:
>> Registers for key and data has also been changed syntax wise to use
>> Verilog two dimensional arrays. All tools (simulators, synthesis/build
>> tools) I have access to including ISE, ModelSim, Quartus parses this
>> correctly.
> Please also see if yosys ( https://github.com/clifford/yosys ) does?

After patching the core-code to use fix the isse with process local two
dimensional arrays synthesis and tech mapping in Yosys completes (after
four hour processing time).

See included result report for cell usage.

Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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