[Cryptech Tech] ICFO Introduction

[Fredrik Thulin]

On torsdag 27 oktober 2016 kl. 12:09:40 CEST Carlos Abellan wrote:
...
> Our entropy source (ES) is also controlled by an FPGA now. We can adapt
> interfacing issues to adapt to the needs of your solution. Currently, the
> format of the random bits is a parallel 8-bit LVDS signal, and we need some
> extra signals to control the ES. All of them can be generated from an
> FPGA.

You can find full schematics for our current board (the Alpha board) here:

  https://wiki.cryptech.is/browser/hardware

(direct link to schematics PDF:
 https://wiki.cryptech.is/browser/hardware/schematics/rev03.pdf )

There are 2x8 GPIO pins from the FPGA exposed on standard 100-mil headers. 
Using them might be a good first step.

The sheet sorting is messed up in that file, see the sheet called 
rev02_19.SchDoc.
 
...
> The final bitrate we can provide depends on the target price. Our optical
> system has been proven up to 42 Gb/s, but then the electronics, ADC and
> processing gets very expensive. What do you think would be an attractive
> RNG bitrate for your HSMs?

Currently the only external noise source connected to the FPGA is an avalanche 
noise based one. It provides input roughly on the order of 1.5 MHz to the FPGA 
which, after conditioning, would be something on the order of 20 kbit/s of 
entropy.

What price point can you get to for such low speeds?

/Fredrik