[Cryptech Tech] Alpha board flash

[Peter Stuge]

Rob Austein wrote:
> If I understand correctly, the current schematics have both hard-wired
> flash for the ARM CPU and also space for an SD card, with the ARM set
> up to boot (only) from the hard-wired flash.

What do you mean by hard-wired flash?


> a) Is this correct?

I'm unsure. The only discrete flash I see in the rev02 schematic are
IC1 (keystore) on sheet 8 and IC3 (FPGA config) on sheet 16.

Other than that, the STM32 has integrated flash memory, but that
isn't shown anywhere in the schematic.


> b) why do we have the SD card ... yet another driver

The SD card might be left over from the initial design with a much
larger CPU.


> c) Why are we using hard-wired flash at all, instead of, eg, just
>    booting from an SD card?

See DM00031020.pdf 2.4 Boot configuration. The ARM can't boot from SD.


> d) If I understand correctly (questionable), SD cards take care of
>    wear leveling.

They do, and that's a bad thing.


> I'm guessing that the hardwired flash envisioned for the Alpha
> board does not, ie, that our driver for the hard-wired flash may
> need to deal with wear-leveling itself.

Again unsure what flash you refer to. In general, NOR flash doesn't
need wear-leveling while NAND does.


> I don't really know how many write cycles we expect the hard-wired
> flash to have, so I'm not sure how serious an issue this is.

NAND flash needs badblocks management from the very first write and
wear-leveling usually comes along with it. NOR typically has 10k-100k
write cycles.


//Peter