[Cryptech Tech] Keeping magic numbers in sync between Verilog and C

[Rob Austein]

Even with the work Paul and I have been doing on a configuration tool
for the core_selector, there are still going to be a lot of magic
numbers buried in .v and .c files.  Having magic numbers in multiple
places usually means they get out of sync.

I'm wondering if it might be practical to declare the .v files
authoritative for such numbers, then write short iverilog programs to
extract those numbers into C header files (and possibly Python files
too while we're at it, but that's a minor frill).  This would also let
the author of the Verilog code declare which magic numbers are
supposed to be exported.

Yes, I know we could just scrape definitions out of .v files using
regular expressions, and we might even decide to do that if the
iverilog route proves too painful, but since we have a perfectly good
Verilog interpreter available, using a real Verilog parser might be
both cleaner and less fragile than the usual regexp-from-hell mess.

Comments?