[Cryptech Tech] NaCL in hardware

[Olof Kindgren]

On Tue, Sep 15, 2015 at 11:27 AM, Павел Шатов <meisterpaul1 at yandex.ru> wrote:
>
>
> On 15.09.2015 11:46, Joachim Strömbergson wrote:
>>
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>> Aloha!
>>
>> Randy Bush wrote:
>>>
>>> how easy is it to move hdl to verilog?  or are there good open
>>> toolsets for hdl?
>>
>>
>> After looking at the source code I'd say its not that hard to do a
>> manual translation to Verilog. Most tools (Xilinx ISE for example)
>> supports both languages. But projects with mixed languages often
>> requires buying a license for that feature.
>>
>> The simulator ModelSim does as far as I know (and Google seems to
>> agree). Not sure about ISE, seems to allow mixed language projects in
>> free version. Pavel surely knows.
>
>
> Yes, you are right, ISE allows both Verilog and VHDL modules in the same
> project.
>
>
>> We would need to wrap the modules to get matching interfaces with what
>> we are using.
>>
>> There are some open VHDL simulators (GHDL, FreeHDL) but not sure how
>> good they are.

All synthesis tool support mixed language. For simulators it's a bit
different. Modelsim requires a special license for that, so not even
all paid versions support it.
Xilinx's toy simulators ISIM (for ISE) and XSIM (for Vivado) both
support mixed-language, but the most interesting solution is probably
to look at the VHDL support that CERN is paying for adding to Icarus
Verilog. Last time I checked a lot of functionality was missing, but I
think it's getting better all the time

//Olof