[Cryptech Tech] dev-bridge board

[Pavel Shatov]

On 20.10.2015 20:57, Basil Dolmatov wrote:
>
>>> Down in the verilog, I notice the fmc_arbiter_cdc module has a 2-cycle
>>> delay "to compensate registered mux delay in user-side logic", but I
>>> haven't traced through enough to understand what that means. Perhaps
>>> Pavel can comment?
>>
>> Well, this particular place configures latency of user-side read logic. I've attached a screenshot from the simulator:
>>
>> 1) first tick: read enable flag gets asserted;
>>
>> 2) second tick: user-side logic detects this flag, core selector decodes address and registers input data;
>>
>> 3) third tick: FMC arbiter captures previously registered data from user-side logic.
>>
>> So, there's 2-cycle delay between assertion of read enable flag and value on input data bus becoming valid.
>>
>> This particular configuration assumes, that our top-level core selector has registered mux. I assume, that you're asking, because this setup is not very convenient for us? If you need core selector to be purely combinatorial (i.e. always @(fmc_addr), not always @(posedge sys_clk)), then this delay should be changed to 1-cycle.
> I would not

Well, yes, 32-bit mux is pretty wide and we have many cores, so 
combinatorial selector can break timing. On the other hand 50 MHz is not 
that fast, but I'd recommend just leaving it as is.

--
With best regards,
Pavel Shatov