[Cryptech Tech] Suggested changes to TRNG

[Bernd Paysan]

Am 6. Oktober 2015 20:01:44 GMT+08:00, schrieb "Joachim Strömbergson" <joachim at secworks.se>:
>It is my guess that this is esp true for the rosc based entropy
>provider
>since the oscillators will always be in a defined state directly after
>FPGA configuration. Letting the oscillators free run for a while before
>starting to collect entropy from them seems prudent to me.

The rosc entropy source's jitter is measured (on the Altera, didn't yet measure the Xilinx) to deliver one good random sample per 128 cycles, so you should a) wait for these 128 cycles after startup, and b) between every readout.

Rushing to read something directly at startup is indeed a bad idea. 

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
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