[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Joachim Strömbergson]

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Aloha!

Rob Austein wrote:
> At Fri, 02 Oct 2015 10:40:01 +0200, Joachim Strömbergson wrote:
>> Rob Austein wrote:
>>> Or violation sets the bit and it stays set until the CPU
>>> performs some kind of explicit reset, eg, sets new flag in the
>>> control word. Either could work, but the latter seems more
>>> robust.
>> How about writing to the status register to clear the error bit?
>> Easy to implement. Lets just do it that way and move forward.
> 
> Um, no, that creates a race condition, because I can only write 
> words, not individual bits.

Not a race condition. But the semantics for the status register changes
from read only to both read and write with write to clear. The other
flags in the register is not affected (cleared) by this. You can write
anything to the register and the error flag will drop.


> Can we please just use the status register for status and the
> control register for control?  I know it's boring, but excitement is
> not really something I'm looking for in an error handling protocol.

;-) Sure I'll play boring. But

The problem I have with this is that now you really need to write
specific bit values, basically do read-modify-write so that the write to
the control register needed to clear the error signal does not effect
any other control bits.

Just to clear confusion:

(1) Some access violation happens -> error bit in STATUS reg is set.

(2) SW writes a <0/1> to error bit in CONTROL reg to clear bit in STATUS
reg.

(3) Error bit is cleared in the next cycle.


This is what you want? What bit value do you want to write?

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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