[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Joachim Strömbergson]

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Aloha!

Rob Austein wrote:
> Or violation sets the bit and it stays set until the CPU performs
> some kind of explicit reset, eg, sets new flag in the control word.
> Either could work, but the latter seems more robust.

How about writing to the status register to clear the error bit? Easy to
implement. Lets just do it that way and move forward.

I guess Paul will be the one most affected by this change. Any
suggestions how you want to roll this Paul?

I can start by creating a branch, "api_error_removal" or somesuch to do
the per-core fixes. I'll start with SHA-1.


> There's a reason why I phrased it as "having a real conversation
> with the FPGA."  Reading a register might be OK.  It's when it
> crosses the line from that to attempting to execute some kind of
> complex recovery behavior that it starts getting to be too much, eg,
> several round trips of reading and writing registers, mucking with
> data structures on the CPU side, etc.

Yes, I think we are in agreement about interrupt handlers.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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