[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Pavel Shatov]

On 01.10.2015 15:32, Joachim Strömbergson wrote:
>
> Most of our HW design has async active low reset (all hash cores, aes,
> cha, trng, entropy providers, parts of eim etc). The big one that does't
> do this is modexp6s.

If you look carefully, you'll see, that this core doesn't have a reset 
signal at all, reset is only used in the wrapper module. I see, that we 
have two voices for active-low and one for active-high. Joachim, can you 
rewrite the wrapper for modexps6 or do you want me to modify it for 
active-low?

>And eim arbiter actually has async
> active high reset, even though the signal is called "eim_cs0_n".

Wait, the signal eim_cs0_n is chip select, and it is indeed active-low. 
Now EIM arbiter has an FSM, that should be reset, when FPGA is 
deselected (i.e. eim_cs0_n == 1'b1), that is why there is posedge in 
that module. Well, I think you can treat this signal as an active-high 
reset, but it is specific to EIM arbiter module, it should not be used 
anywhere else.

> Since we have previously gone for async active low and by far most of
> our design uses this strategy, I propose that we use async active low
> reset (with synch deassertion). Where platform specific FPGA macros
> require something different we solve that in each case, preferably in a
> wrapper.

Joachim, one more important thing to consider is the clock manager 
module. We have a PLL there, so we must wait for it to lock before 
releasing reset. PLL has an active-high output named LOCKED. In theory 
this signal can be directly used as reset, but I remember, that doing so 
gives very weird timing issues, that's why I added a synchronizer there. 
This synchronizer looks like Fig.7 from this document:

http://www.xilinx.com/support/documentation/white_papers/wp272.pdf

where Asynchronous_Reset is in fact LOCKED output of PLL.

Right now `sys_rst' (which is generated by clock manager) behaves 
exactly as you want: it gets asserted asynchronously whenever PLL has no 
lock, and then released synchronously. The only problem is polarity, 
since I coded it to be active-high. To convert it to active-low, you 
need to preload the shift with register with zeroes instead of ones, and 
feed 1 instead of 0 into the first flip-flip. Do you want me to modify 
novena_clkmgr.v or you can handle this yourself?

--
With best regards,
Pavel Shatov