[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Rob Austein]

At Wed, 30 Sep 2015 19:04:29 -0400, Paul Selkirk wrote:
> On 09/29/2015 08:12 AM, Rob Austein wrote:
...
> >   We could of course just generate a static address map for the C code
> >   at build time, but that has its own form of fragility (tighter
> >   coupling between rtl and sw than would otherwise be necessary).
> 
> The problem is that you can't assume that what's running on the FPGA was
> built from the same configuration that's on your hard disk. Which I
> think is what you're saying.

Yep.

> > Last: it's not obvious to me that this dynamic configuration mechanism
> > really belongs in core/platform/novena, it seems likely to end up
> > being more general than that.
> 
> You're right on all counts. The one caveat is that the core_selector
> ports (names and widths of signals) are platform-specific, if not
> strictly Novena-specific.

So we template the upper interface of core_selector too, or come up
with a standard interface between the very top module and
core_selector, or something.  Not worried.  Deal with it when we have
concrete changes we need to make.