[Cryptech Tech] [Cryptech-Commits] [core/platform/novena] 21/21: Sick hacks to compensate for sparse MUX within TRNG core.

[Bernd Paysan]

Am 1. Oktober 2015 03:38:56 GMT+08:00, schrieb Pavel Shatov <meisterpaul1 at yandex.ru>:
>On 30.09.2015 8:32, Bernd Paysan wrote:
>> Am 30. September 2015 01:54:03 GMT+08:00, schrieb Randy Bush
>> <randy at psg.com>:
>>
>>         1) Just leave everything as it is right now with mixed
>resets.
>>
>>         2) We start a voting process and decide, what kind of reset
>we
>>         will be
>>         using from now on. Everyone will then modify his cores
>accordingly.
>>
>>         3) Someone will take responsibility and decide for the whole
>>         team, what
>>         kind of reset is the right one for us. Again everyone will
>then
>>         modify
>>         his cores accordingly.
>>
>>
>>     you, rob, and joachim please crawl in a corner, discuss, and
>declare
>>     result.
>>
>>     randy
>>    
>------------------------------------------------------------------------
>>
>>     Tech mailing list
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>>
>>
>> I don't know where this religious part about resets originates from;
>in
>> reality, your average ASIC and FPGA flip-flop has an async active low
>> input for reset. Using that means least amount of resources and
>> confusion.
>
>I don't know, whether Spartan-6 is an average FPGA or not, but its 
>flip-flops (and virtually all other primitives) have active-high reset,
>
>so least amount of confusion will be, when all internal resets are 
>active-high.

Yes, Xilinx is the exception, the other FPGA vendors have a closer match to ASIC libraries. It also offers a configuration for synchronous or asynchronous, whereas the competition uses the LUT for sync reset. If you design for general usefulness, you don't design for Xilinx, but for some common ground. And that's async, active low. Active low is not so strictly required, because all these synthesis tools can handle the inverter, but you should have a convention to avoid confusion when wiring modules together.

>> Of course, you must not activate the clock before reset goes away
>> (easy). But for sync reset, it's just the other way round: you must
>make
>> sure there is an active clock before reset goes away, which is about
>the
>> same effort. For I/Os with a defined value at startup, async is the
>only
>> possible choice. And active low, because 0V is the only reliably
>> available voltage at startup (not applicable for FPGAs).
>>
>> The reset is only for startup, never for active circuit logic (unless
>> you really know what you are doing ;-), therefore, every later
>> transition must be synchronous.
>
>Reset is not strictly required for startup in an FPGA, since you can 
>write something like reg x = 1'b0 or reg y = 1'b1. Some people still 
>prefer to assign default values to registers using reset, but again 
>there's no point in doing it asynchronously.

Yes, in an FPGA, you have that option. In an ASIC, no. So it is not generally useful.

The reason for async reset is that you don't need a clock to get your device into a default stable state, and it also works, when reset goes away before the clock starts. This is not something you always need, but when you do, sync is no option. On the other hand, async has no such show-stopper disadvantage.

In both cases, you need a similar logic to make sure that there is no conflict between clock and reset. And if you want sync reset, this logic needs an async reset.

I speak with the experience of having converted two Xilinx-specific designs for an ASIC. Any Xilinx-specific approach for me is a mistake. 

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
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http://bernd-paysan.de/