[Cryptech Tech] dev-bridge board

[Pavel Shatov]

On 01.11.2015 21:30, Paul Selkirk wrote:

> As an aside, I took some performance numbers for 2 million reads and
> writes to a dummy register through libhal:
> read:  3.363 seconds,  594707/sec
> write: 2.127 seconds,  940291/sec
>
> By contrast, EIM is rather faster:
> read:  1.774579 seconds, 1127027/sec
> write: 1.696443 seconds, 1178937/sec
>
> I haven't done any analysis yet, just presenting the numbers I
> collected. In any case, I don't think the bus is going to be the
> bottleneck when we're talking to cores that are actually doing something.

I see, that while writing is only ~20% slower, reading is ~2X as slow. 
This must be because of my double-reading hack I used to overcome NWAIT 
hardware bug in STM32.

Another thing to note is that inside of CMSIS wrappers 
HAL_SRAM_Read_32b() and HAL_SRAM_Write_32b() there's supporting code to 
lock/unlock HAL, update memory state, etc. I think, this code also 
imposes some overhead.


> To do:
> - merge activelow branch

I think, as I tried to push to that branch earlier, I screwed up and 
accidentally just created a copy of the master branch named activelow 
without any changes. Should be fixed now.


--
With best regards,
Pavel Shatov