[Cryptech Tech] core size in cryptech.h

[Joachim Strömbergson]

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Aloha!

Thanks!

Paul will you update this document or shall I?

Шатов Павел wrote:
> 
> 
> Отправлено из мобильной Яндекс.Почты: http://m.ya.ru/ymail
> 
> 11:25, 4 мая 2015 г., "Joachim Strömbergson" <joachim at secworks.se>:
> 
> 
> 
> Aloha!
> 
> Павел Шатов wrote:
> 
> Speaking of core sizes, as far as I remember, we wanted to have 
> different segments for different types of cores. All hashes can be in
> one segment and have the same size. ECDSA is a signature core, we can
> place it in a different segment, where all cores will have different
> size and so on.
> 
> Yes. And as long as we don't run out of address space in a segment I 
> think grouping cores makes sence. We have five out of eight possible 
> segments allocated so we do have a lot of headroom still. The
> globals segment could probably be squeezed a bit if it starts getting
> cramped. But for now I think we should just use what we have. As long
> as we can have the core sizes a bit different for modexp, ecdsa for
> example.
> 
> We could also bikeshed a bit about if math is the best name for the 
> segmemt that supports rsa, ecdsa. I don't know how generic re curves 
> your core. But for modexp the name works.
> 
> One similar issue is cipher modes. Having things like ctr, gcm in 
> ciphers is straight forward. But should keywrap also be there. And
> for keywrap I would appreciate thoughts from you, Rob, Paul and
> anyone else how the use case should be.
> 
> Basically we want to be able to write read and write wrapped keys
> and wrap/unwrap keys stored in RAM inside the FPGA. But we then would
> also like to be able to send unwrapped keys to the other cores (or
> have them read from a common key memory.) (Having the CPU transfer
> the unwrapped keys would make the wrapping rather meaningless ;-)
> 
> This might mean that we need to add an internal top level
> controller/DMA unit (which could have addresses in the globals.)
> inside the FPHA. The controller can perform read/writes on the
> internal bus for us. Or some other mechanism. Thie controller would
> then also be able to access addresses the CPU can't.
> 
> Joachim, we really need to write down what cores we have right now. 
> Can you update that memory map, that I created along with baseline 
> project?
> 
> Sure. I will update the cryptech.h and the RTL with all cores (aes, 
> chacha are the main ones not in there). Where is the document in the 
> repo?
> 
> 
> http://wiki.cryptech.is/browser/test/novena_base/doc/EIM_Memory_Map.doc
>
>  Download the .doc file.
> 
> 
> 
> - -- Med vänlig hälsning, Yours
> 
> Joachim Strömbergson - Alltid i harmonisk svängning. 
> ========================================================================
>
> 
Joachim Strömbergson          Secworks AB          joachim at secworks.se
> ========================================================================
>
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> 
> 


- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
========================================================================
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