[Cryptech Tech] Low level side channels

[Joachim Strömbergson]

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Aloha!

Fredrik Thulin wrote:
> Integrering text on low level side channels in x86.
> 
> How is an ARM A9 in this aspect? M3?
> 
> http://blog.erratasec.com/2015/03/x86-is-high-level-language.html?m=1

Good
> 
read, but should not be that surprising since the x86 is a CISC.

Since the PPro, the CPU is actually a RISC-like, superscalar OOO engine
with a CISC to RISC (uops) translation engine in front of it. And the
important thing is that from generation to generation, Intel both
updates the infrastructure for doing faster decoding (with bigger and
better uops caches) as well as updating the CISC x86 ISA -> RISC uops
translation.

This means that the number of uops as well as the specific uops a given
x86 instruction is mapped to may differ from generation to generation.
This can cause changes in timing for an x86 instruction and add
execution time variance for code that might have been considered
variance immune. The uops caches makes the situation even harder to predict.

See for example this article about the Hasweel microarchitecture:
http://www.anandtech.com/show/6355/intels-haswell-architecture/14

Note the uop caches.

The ARM microarchitectures don't really have the same setup and is
easier to predict. What you do have in for example Cortex M3 is a
decoder for Thumb-type instructions. The ARM9 is a dual issue OOO CPU
which means that it is harder to predict execution time than the M3. The
Cortex M3 and M4 are ARMv7 based CPUs which means single issue with a
simple pipeline.

A good preso with the different ARM instruction sets, microarchitectures
etc:
http://www.eit.lth.se/fileadmin/eit/courses/eitf20/ARM_RG.pdf

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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