[Cryptech Tech] Restricting FPGA signing

[Fredrik Thulin]

On Wednesday, January 28, 2015 03:49:25 PM Jakob Schlyter wrote:
> To be able to implement "content inspection" of data to be signed, Joachim
> and I talked about having the FPGA hasher/signer work in two different
> modes:
> 
> - Permissive mode: FPGA happily signs anything the ARM feeds it
> - Restricted mode: FPGA signs only hashes for data previously consumed
> 
> This way the content inspection can be implemented in the ARM only (once the
> FPGA is set to restricted mode). If data is passed to the FPGA for hashing,
> it may also (at some later point depending on what PKCS#11 mechs are used)
> sign it (but the ARM doesn't need to care about that).
> 
> WDYT?

Good thinking, but maybe feature creep I think. At least for early 
implementation. I'm thinking design to accommodate it, but save implementation 
for v > 1.

To be honest, this prioritizing comes from my own inability to code a checker 
in Verilog.

/Fredrik