[Cryptech Tech] goals / use cases

[Joachim Strömbergson]

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Aloha!

Randy Bush wrote:
> Peter Gutmann wrote:
>> I know that's the theoretical answer, but how would you
>> side-channel AES or SHA-1?  For DSA and ECDSA, which are a whole
>> smorgasbord of side-channel opportunities, I can see this would be
>> an issue (thus the comment about leaving that for an FPGA), but any
>> side-channel on AES is going to be something like leaking the key
>> via EMI, in which case an FPGA can do exactly the same thing.
> 
> that is our code in the fpga, and not our code in the arm.

And that is exactly the difference. Since it is our code we can try
different methods at protecting against side channel leakage.

There are many ways to try (as the number of papers with side channel
protection mechanisms presented at CHES shows.)  We might not succeed,
and somebody will probably find ways to defeat what we do (as the number
of papers on better side channel attacks presented at CHES shows.)

The important thing is that we have that ability, and can even change
protection mechanisms as time goes by. With a hard core in the CPU there
is no ability to do that.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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