[Cryptech Tech] Short note on the current FPGA activities

[Joachim Strömbergson]

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Aloha!

Basil Dolmatov wrote:
> All cores should have standard bus interface and we need addressing 
> table for this bus for all cores we create and use. Something like 
> /etc/services ;)

All cores have a standard (or at least a common) interface. They are in
fact very suitable for being used as coprocessors to a ARM. Basically
32-bit register read/write.

The big problem is that the cores are generally big endian and ARM
generally is lttle endian. (Yes you can change the endianess in ARM, but
nobody does and who nows what SW will break if you do.)

I agree that developing a common address table would be good. Different
versions of crypteh could just have holes in the mapping if a
core/feature is missing. I would suggest then that there is an area in
the memory map that always contains a description of the features.
(All cores also has a couple of words with type, version info.)

But this is based on the idea that we actually do use the FPGA on a
register address mapping. We could instead have something that just
handles command/response on a functional level.

I.e. instead of saying:
  write 0xdeadbeef to address
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