[Cryptech Tech] FPGA for alpha board

[Basil Dolmatov]

In any case it should be bus between these two parts of design and these parts will definitely belong to different clock domains. 
So, I cannot see drastic performance difference (except we will choose either too slow ARM or too slow FPGA core)

The only difference seen for me now  is the absence of external wires between these two parts, if CPU part will reside in the same FPGA crystal. Do not see any advantages from that. 

dol@ с iPad

> 11 янв. 2015 г., в 23:53, Joachim Strömbergson <joachim at secworks.se> написал(а):
> 
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> Aloha!
> 
> Yes, adding a soft core is one option we have for the future. Using a
> hard core such as Xilinx Zync or Altera SoCs adds a lot of performance,
> but it reduces the ability to actually test and know as well as limit
> what is actually accessible from where.
> 
> In terms of side channel leakage, having an internal interface on chip
> is better than having an interface over the PCB. But this interface will
> be inside the tamper boundary.
> 
> For the next, next generation board (or later revisions of this one) we
> may move to an integrated solution. But for the platform after Novena I
> think our assumption right now is that we really want to have separate
> physical devices. This is because it allows us to decompose the system
> into separate partitions that can more easily be controlled and audited.
> 
> Cheers
> JoachimS
> 
> Шатов Павел wrote:
>> Hello everyone. I haven't attended your meeting, so I don't know all
>> the underlying details of your discussion. Do you intentionally want
>> your board to include CPU and FPGA as two separate chips? As far as I
>> know in terms of hardware security having one single integrated
>> circuit is better. Two options are possible to combine both CPU and
>> FPGA in one physical IC. The first option is to select larger FPGA
>> and add some processor IP core to it. Both Altera and Xilinx provide
>> soft processors, but they are not opensource. I believe there might
>> be suitable soft processors available at 
>> http://opencores.org/projects. The drawback of this approach is that
>> such soft processors will not run very fast. I've mostly worked with
>> Spartan-6, from my experience it is difficult to push MicroBlaze from
>> Xilinx beyond 125-133 MHz. Other processors should be about the same.
>> On the other hand you can configure soft processor to only include
>> modules that you actually need. The second option is to use some PSoC
>> chip. I can suggest having a look at Zynq from Xilinx: 
>> http://www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-table.pdf.
>> It has dual-core ARM Coretex-A9 CPU and Artix/Kintex FPGA in one
>> package. There are several other PSoC vendors too, Zynq is just an
>> example. From my experience programmable system-on-chip projects
>> require much initial effort, but as the project matures it becomes
>> easier to develop 
>> it.<http://www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-table.pdf>
> 11.01.2015, 12:18, "Fredrik Thulin" <fredrik at thulin.net
>> <mailto:fredrik at thulin.net>>:
>>> 
>>> It seems to me that the interface between the FPGA and ARM will be
>>> one of the real selectors for what ARM to use?
>>> 
>>> Joachim, can you make a baseline suggestion for what FPGA to use
>>> and what interface to use?
>>> 
>>> I remember from the meeting last week that we said we are currently
>>> using about 70% of the resources in the Novena FPGA and would aim
>>> for something 10x (?) bigger for the alpha board, to not be space
>>> constrained during development?
>>> 
>>> /Fredrik
>>> 
>>> _______________________________________________ Tech mailing list 
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>>> https://lists.cryptech.is/listinfo/tech
>> -- With best regards, Paul Shatov
>> 
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> 
> 
> - -- 
> Med vänlig hälsning, Yours
> 
> Joachim Strömbergson - Alltid i harmonisk svängning.
> ========================================================================
> Joachim Strömbergson          Secworks AB          joachim at secworks.se
> ========================================================================
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