[Cryptech Tech] arm

[Joachim Strömbergson]

Aloha!

And i2c, usart, spi adds a number of cycles of latency just for mux/demux of data at respective endpoint. This will add to the response time for some possible operations requested by a host.

Sent from my iPhone

> On 11 Jan 2015, at 19:25, Hannes Tschofenig <hannes.tschofenig at gmx.net> wrote:
> 
> It might be good to know how much data you want to exchange.
> 
> The I2C bus exchanges data at a rate up to 1 Mbit/s.
> 
> The chips typically come with a number of other interfaces as well. For
> example, USART (11.25 Mbits/s) and SPI (45 Mbits/s) interfaces.
> 
> The speed will vary across chips.
> 
>> On 01/11/2015 05:46 PM, Basil Dolmatov wrote:
>> Concerning _operational_tasks_ (not RNG debugging) I wonder why we need faster interface? 
>> 
>> dol@ с iPad
>> 
>> 11 янв. 2015 г., в 19:30, Randy Bush <randy at psg.com> написал(а):
>> 
>>>>> Again, what's the interface to the FPGA?
>>>> I2C?
>>> 
>>> can't find anything slower?
>>> 
>>> fwiw, we've been through weeks of debug to move off i2c to eim.
>>> 
>>> randy
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