[Cryptech Tech] Alpha board strategy

[Bernd Paysan]

Am Mittwoch, 18. Februar 2015, 05:31:51 schrieb Randy Bush:
> >> More specifically the C7 version:
> >> http://www.altera.com/literature/hb/cyclone-v/cv_51001.pdf
> >> 
> >> This device provides 150k logic elements, which is a bit more than 2x
> >> the amount provided by the Xilinx Spartan-6 LX45 on the Novena (if we
> >> allow us to do some apples and pears comparison). We would like to have
> >> the C9 device since it would give us headroom to handle all we think we
> >> want to put in the FPGA with room to spare.
> > 
> > Cool. That should be big enough to fit a CHERI CPU. As I mentioned
> > before, I think this is a better option than ARM on account of having
> > a far better memory protection model. Also means you don't have to
> > rely on the CPU being honest (if you believe its hard to subvert an
> > FPGA, that is).
> 
> the philosophy seems eminently sensible, but ...
> 
> if we want to keep under the pay-for-license ceiling, we are on a tight
> LE budget.  this puts us in a nasty trade-off space.  how many LE does
> a cheri cpu eat?

If you want a low-cost CPU, a b16 costs you somewhere between 600 and 800 LEs 
(depending whether you enable the debugging interface).

If you need security boundaries between different tasks, just instantiate 
another CPU...  This is much better than a complicated memory protection 
model: You are 100% sure CPU A can't write into CPU B's memory, nor can CPU A 
hog CPU B's compute time.

Of course, you can't compile some fancy C library on the b16.

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://bernd-paysan.de/
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