[Cryptech Tech] First hash via EIM

[Joachim Strömbergson]

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Aloha!

Шатов Павел wrote:
> Yes, I've tried compiling the project and saw that warning, that
> sys_eim_rd is not used. Paul, in my baseline project I've included a
> testbench (tb_demo_adder.v) that simulates complete demo adder core
> operation. It writes X and Y operands, modifies control register to
> trigger addition, then polls status register and reads Z=X+Y register
> from the adder core. This testbench has two tasks, namely eim_write
> and eim_read, that simulate write and read transactions from the CPU.
>  You can modify the original testbench to debug operation of your
> cores, if you need.

That would be to test the EIM interface connectivity and the core
selector should have a testbench that checks that it works. All old
cores (sha256 for example) have separate self-testing testbenches on
core as well as top level with the memory like interface.


> Please have a look at the attached pictures: sys_eim_addr,
> sys_eim_wr, sys_eim_rd and sys_eim_dout are asserted simultaneously
> (sys_eim_dout is only assigned during write transactions). Flags
> become active for one cycle, so our cores should handle transactions
> as soon one of the flags is set. During read transaction arbiter
> internally delays read flag (sys_req_dly signal in the waveforms) for
> one additional cycle to allow user logic to place read value into 
> eim_data_in register. This value is then latched and sent to the CPU.
> If our cores have registered outputs, then core multiplexor should be
> non-pipelined to match latency expected by EIM arbiter. If pipelined
> multiplexor is needed, then one more bit should be added to
> sys_req_dly to increase arbiter latency by one cycle. Pipelined
> multiplexor consumes more slices, but makes meeting internal timing
> constraints easier. I'll take a closer look at this issue tomorrow. I
>  should be not very difficult to fix it.

I don't think that there are an issue to fix at the moment. We meet
timing with ns to spare. But it is good to know that we could
potentially add a delay cycle for read operations.

Note that I've changed the names slightly to instead talk about read and
write data. It becomes fairly confusing when an input port is called
output-something.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
========================================================================
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