[Cryptech Tech] dev-bridge board

[Paul Selkirk]

Current status: I have a stable build/test environment for the
dev-bridge board. Everything is in the sw/stm32 repo. This builds
Fredrik's board self-tests "natively", and builds Rob's libhal tests
with a thin wrapper around main(), and some missing libc support functions.

For Prague, Rob wrote a small PKCS #11 library, which ran on the Novena,
and talked through libhal to the FPGA cores.

We are currently hashing out a libhal RPC mechanism to allow a PKCS #11
application running on a host to talk to the STM32 (and thus the FPGA)
over USB.

I have a few questions I'm not qualified to answer, because I don't
understand the board well enough.

1) I'm currently using the USB as a UART. On the host side, I read and
write bytes over /dev/ttyUSB0. Is this sufficient/acceptable, or should
we try to use the USB Device interface? And if we do that, what device
class? 0x0B Smart Card, I guess? But that path ends in implementing a
CCID or PC/SC interface on the device, so I'd rather avoid that.

2) Can we use a portion of the ARM internal flash memory for data
storage? If so, what address range?

3) How do we access the Master Key Memory? I see that it's a 23K640-I/SN
64K SPI Bus Low-Power Serial SRAM. Is there code to talk to it?
HAL_SPI_MODULE_ENABLED is not defined in the default HAL configuration.

4) Looking further down the road, is there code or documentation for the
AVR tamper detect MCU? I can't help noticing that there are 8 exposed
GPIO headers for the AVR. Will those be used for an external tamper
circuit, or is this the back door to the MKM?

5) What are all these extra power headers? Are they for the alpha board,
against the day when it's no longer tethered to the Novena?

Looking for clarity...

				paul