[Cryptech Tech] cryptlib HAL for EIM

[Павел Шатов]

On 22.04.2015 19:11, Paul Selkirk wrote:
> The EIM version of the cryptlib HAL is done (the glue that lets cryptlib
> talk to the cryptech cores over EIM). Actually, the first version was
> done a couple weeks ago, but I neglected to post about it. It passes
> 'make test', which means it does some hashes and generates some RSA keys.

That's great, Paul!

> Questions:
>
> (Mainly for Joachim and Pavel)
> a) Does this unified memory map make sense to you? One thing that's lost
> in the translation from 17-bit EIM addresses to 16-bit I2C addresses is
> 1 bit from the core selector (6 bits down to 5), but I don't forsee
> having more than 32 cores in any given segment.

I don't know whether this 1 bit is important or not. If you remember, 
EIM arbiter initially had smaller address bus, Joachim then asked me to 
take advantage of 3 additional address lines, that bunnie routed in 
Novena. Joachim, can we sacrifice 1 address bit?

One thing that actually bothers me is documentation. I created draft 
memory map along with baseline EIM project. It had addresses and 
descriptions of all the registers for SHA cores. Since then several new 
cores were added and existing cores were rearranged. Can we document all 
this somehow? We can either update my document or create new one from 
scratch. I believe, if we want other people to be able to use our 
platform, we should provide documentation. This documentation should 
include description of how core segments are arranged and how core 
selector works. All the available registers should be listed along with 
addresses, access types and descriptions. Without such documentation, 
people will have to figure out how core selector works, and then dig 
into Verilog sources of individual cores to find out, what exactly 
specific registers are used for.

--
With best regards,
Pavel Shatov