[Cryptech Tech] Dieharder test of Cryptech RNG data

[Павел Шатов]

On 04.04.2015 13:24, Joachim Strömbergson wrote:
>
> Aloha!
>
> Павел Шатов wrote:
>> What's wrong with electrical schematics?
>
> Because at least for the FPGA, we don't have access to the electrical
> level. I can and will produce documentation that shows how an oscillator
> is mapped onto slices etc. (post placement information). But beyond that
> we are in the dark. We could work all the way down to switching and
> GDSII-format, but that does not show how the FPGA vendor actually
> implements the gates, regs etc on an electrical level.
>

Joachim, I was specifically talking about avalanche noise circuit. About 
transistors, resistors, capacitors and so on. Not about FPGA internals, 
of course.

--
With best regards,
Pavel Shatov